PC87309VLJ datasheet(14/192 Pages) NSC

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Signal/Pin Connection and Description

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CFG0

Conﬁguration

Input

Group 4

This pin selects between Full-IR and Two-UART mode as the default

configuration upon power up. It is pulled down by internal 30 K

Ω

resistors. External 10 K

Ω pull-up resistors to V

DD should be

employed.

This signal is multiplexed with SOUT1.

See TABLE 2-1 and Section 2.1.

CLKIN

Clock

Input

Group 1

Clock In – A TTL or CMOS compatible 48 MHz clock.

CTS2,1

93,83

UART1,

UART2

Input

Group 1

UART1 and UART2 Clear to Send – When low, these signals indicate

that the modem or other data transfer device is ready to exchange data.

CTS2 is multiplexed with A11, and available only in Two-UART mode.

D7-0

8-1

ISA-Bus

I/O

Group 5

ISA-Bus Data – Bidirectional data lines to the microprocessor. D0 is

the LSB and D7 is the MSB. These signals have 24 mA (sink)

buffered outputs.

DACK3

DACK2,1

39,38

ISA-Bus

Input

Group 1

DMA Acknowledge 1,2 and 3 – These active low input signals

acknowledge a request for DMA services and enable the IOWR and

IORD input signals during a DMA transfer. These DMA signals can be

mapped to the following logical devices: FDC, UART or Parallel Port.

DCD2,1

94,84

UART1,

UART2

Input

Group 1

UART1 and UART2 Data Carrier Detected – When low, this signal

indicates that the modem or other data transfer device has detected

the data carrier.

DCD2 is multiplexed with P12 and available only in Two-UART mode.

DENSEL

97, 48 or

FDC

Output

Group 11

Density Select – Indicates that a high FDC density data rate (500

Kbps or 1 Mbps) or a low density data rate (250 or 300 Kbps) is

selected.

DENSEL polarity is controlled by bit 5 of the SuperI/O FDC

Conﬁguration register as described in Section 2.5.1.

This signal is multiplexed with: IRTX, , DR1, or R12.

DIR

FDC

Output

Group 11

Direction – This output signal determines the direction of the Floppy

Disk Drive (FDD) head movement (active = step in, inactive = step

out) during a seek operation. During reads or writes, DIR is inactive.

DR1,0

48, 47

FDC

Output

Group 11

Drive Select 0 and 1 – These active low output signals are the

decoded drive select output signals. DR0 and DR1 are controlled by

Digital Output Register (DOR) bits 0 and 1. They are encoded with

information to control four FDDs when bit 7 of the SuperI/O FDC

Conﬁguration register is 1, as described in Section 2.5.1.

DR0 can optionally become a logical OR of DR0 and MTR0 when

MTR0/DRATE0 is used as DRATE0.

DR1 is multiplexed with DENSEL and is available only in Two-UART

mode. Optionally, it can become a logical OR of DR1 and MTR1

when MTR1/P12 is used as P12.

See MTR0,1 for more information.

DRATE0

95, 45 or

FDC

Output

Group 14

Data Rate 0 – This output signal reflects the value of bit 0 of the

Conﬁguration Control Register (CCR) or the Data Rate Select Register

(DSR), whichever was written to last. Output from the pin is totem-pole

buffered (6 mA sink, 6 mA source).

This signal is multiplexed with IRRX1/P12, MTR0 or DSR2

DRQ3-1

37-35

ISA-Bus

Output

Group 13

DMA Request 1, 2 and 3 – These active high output signals inform

the DMA controller that a data transfer is needed. These DMA signals

can be mapped to the following logical devices: Floppy Disk Controller

(FDC), UART or parallel port.

DSKCHG

FDC

Input

Group 1

Disk Change – This input signal indicates whether or not the drive

door has been opened. The state of this pin is available from the

Digital Input Register (DIR). This pin can also be conﬁgured as the

RGATE data separator diagnostic input signal via the MODE

command. See the MODE command in Section 3.7.7.

Signal/Pin

Name

Number

Module

I/O and

Group #

Function

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