PC87309VLJ datasheet(43/192 Pages) NSC

43 / 192 page

The Floppy Disk Controller (FDC) (Logical Device 0)

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3.3.6

Data Rate Select Register (DSR)

This write-only register is used to program the data transfer

rate, amount of write precompensation, power down mode,

and software reset.

The data transfer rate is programmed via the CCR, not the

DSR, for PC-AT, PS/2 and MicroChannel applications. Oth-

er applications can set the data transfer rate in the DSR.

The data rate of the floppy controller is determined by the

most recent write to either the DSR or CCR.

The DSR is unaffected by a software reset. A hardware re-

set sets the DSR to 02h, which corresponds to the default

precompensation setting and a data transfer rate of 250

Kbps.

Bits 1,0 - Data Transfer Rate Select

These bits determine the data transfer rate for the Flop-

py Disk Controller (FDC), depending on the supported

speeds. TABLE 3-5 shows the data transfer rate select-

ed by each value of this field.

These bits are unaffected by a software reset, and are

set to 10 (250 Kbps) after a hardware reset.

TABLE 3-5. Data Transfer Rate Encoding

Bits 4-2 - Precompensation Delay Select

This field sets the write precompensation delay that the

Floppy Disk Controller (FDC) imposes on the WDATA

disk interface output signal, depending on the supported

speeds. TABLE shows the delay for each value of this

field.

In most cases, the default delays shown in TABLE 3-7

are adequate. However, alternate values may be used

for specific drive and media types.

Track 0 is the default starting track number for precom-

pensation. The starting track number can be changed

using the CONFIGURE command.

TABLE 3-6. Write Precompensation Delays

TABLE 3-7. Default Precompensation Delays

Bit 5 - Undeﬁned

Should be set to 0.

Bit 6 - Low Power

This bit triggers a manual power down of the FDC in

which the clock and data separator circuits are turned

off. A manual power down can also be triggered by the

MODE command.

After a manual power down, the FDC returns to normal

power after a software reset, or an access to the Data

0: Normal power.

1: Trigger power down.

Bit 7 - Software Reset

This bit controls the same kind of software reset of the

FDC as bit 2 of the Digital Output Register (DOR). The

difference is that this bit is automatically cleared to 0 (no

reset) 100 nsec after it was set to 1.

See also “Bit 2 - Reset Controller” on page 40.

0: No reset. (Default)

1: Reset.

3.3.7

Data Register (FIFO)

The Data Register of the FDC is a read/write register that is

used to transfer all commands, data and status information

between the microprocessor and the FDC.

During the command phase, the microprocessor writes

command bytes into the Data Register after polling the

RQM (bit 7) and DIO (bit 6) bits in the MSR. During the re-

sult phase, the microprocessor reads result bytes from the

Data Register after polling the RQM and DIO bits in the

MSR.

DSR Bits

Data Transfer Rate

500 Kbps

300 Kbps

250 Kbps

1 Mbps

76543210

Reset

Required

Data Rate Select

Offset 04h

Precompensation Delay Select

Undefined

Low Power

Software Reset

Data Transfer Rate Select

Write Operations

DSR Bits

Duration of Delay

432

Default (TABLE 3-7)

41.7 nsec

83.3 nsec

125.0 nsec

166.7 nsec

208.3 nsec

250.0 nsec

0.0 nsec

Data Rate

Precompensation Delay

1 Mbps

41.7 nsec

500 Kbps

125.0 nsec

300 Kbps

125.0 nsec

250 Kbps

125.0 nsec

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