PC87309VLJ datasheet(44/192 Pages) NSC

44 / 192 page

The Floppy Disk Controller (FDC) (Logical Device 0)

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Use of the FIFO buffer lengthens the interrupt latency peri-

od and, thereby, reduces the chance of a disk overrun or

underrun error occurring. Typically, the FIFO buffer is used

at a 1 Mbps data transfer rate or with multi-tasking operating

systems.

Enabling and Disabling the FIFO Buffer

The 16-byte FIFO buffer can be used for DMA, interrupt, or

software polling type transfers during the execution of a

read, write, format or scan command.

The FIFO buffer is enabled and its threshold is set by the

CONFIGURE command.

When the FIFO buffer is enabled, only execution phase byte

transfers use it. If the FIFO buffer is enabled, it is not dis-

abled after a software reset if the LOCK bit is set in the

LOCK command.

The FIFO buffer is always disabled during the command

and result phases of a controller operation. A hardware re-

set disables the FIFO buffer and sets its threshold to zero.

The MODE command can also disable the FIFO for read or

write operations separately.

After a hardware reset, the FIFO buffer is disabled to main-

tain compatibility with PC-AT systems.

Burst Mode Enabled and Disabled

The FIFO buffer can be used with burst mode enabled or

disabled by the MODE command.

In burst mode, the DRQ or IRQ signal assigned to the FDC

remains active until all of the bytes have been transferred to

or from the FIFO buffer.

When burst mode is disabled, the appropriate DRQ or IRQ

signal is deactivated for 350 nsec to allow higher priority

transfer requests to be processed.

FIFO Buffer Response Time

During the execution phase of a command involving data

transfer to or from the FIFO buffer, the maximum time the

system has to respond to a data transfer service request is

calculated by the following formula:

Max_Time = (THRESH + 1) x 8 x tDRP – (16 x tICP)

This formula applies for all data transfer rates, whether the

FIFO buffer is enabled or disabled. THRESH is a 4-bit value

programmed by the CONFIGURE command, which sets

the threshold of the FIFO buffer. If the FIFO buffer is dis-

abled, THRESH is zero in the above formula. The last term

in the formula, (16 x tICP) is an inherent delay due to the mi-

crocode overhead required by the FDC. This delay is also

data rate dependent. Section 10.3.14 on page 183 specifies

minimum and maximum values for tDRP and tICP.

The programmable FIFO threshold (THRESH) is useful in

adjusting the FDC to the speed of the system. A slow sys-

tem with a sluggish DMA transfer capability requires a high

value for THRESH. this gives the system more time to re-

spond to a data transfer service request (DRQ for DMA

mode or IRQ for interrupt mode). Conversely, a fast system

with quick response to a data transfer service request can

use a low value for THRESH.

3.3.8

Digital Input Register (DIR)

This read-only diagnostic register is used to detect the state

of the DSKCHG disk interface input signal and some diag-

nostic signals. DIR is unaffected by a software reset.

The bits of the DIR register function differently depending

on whether the FDC is operating in PC-AT drive mode or in

PS/2 drive mode. See Section 3.1.2 on page 34.

In PC-AT drive mode, bits 6 through 0 are in TRI-STATE to

prevent conflict with the status register of the hard disk at

the same address as the DIR.

Bit 0 - High Density (PS/2 Drive Mode Only)

In PC-AT drive mode, this bit is reserved, in TRI-STATE

and used by the status register of the hard disk.

In PS/2 drive mode, this bit indicates whether the data

transfer rate is high or low.

0: The data transfer rate is high, i.e., 1 Mbps or 500 Kbps.

76543210

Reset

Required

Data Register

(FIFO)

Offset 05h

Data

76543210

Reset

Required

Digital Input

Offset 07h

DSKCHG

Reserved, In TRI-STATE

Read Operations, PC-AT Drive Mode

76543210

Reset

Required

Digital Input

Offset 07h

DRATE1 Status

DSKCHG

DRATE0 Status

Reserved

High Density

Read Operations, PS/2 Drive Mode

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