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PC87309VLJ データシート(PDF) 93 Page - National Semiconductor (TI) |
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PC87309VLJ データシート(HTML) 93 Page - National Semiconductor (TI) |
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93 / 192 page  Parallel Port (Logical Device 1) 93 www.national.com Bits 7-3 - Reserved These bits are treated as 0 for offset calculations. Writ- ing any other value to them has no effect. These bits are read only. They return 00000 on reads and must be written as 00000. 4.5.14 ECP Extended Data Register (EDR) This read/write register is the data port of the control regis- ter indicated by the index stored in the EIR. Reading or writ- ing this register reads or writes the data in the control register whose second level offset is specified by the EIR. Bits 7-0 - Data Bits These read/write data bits transfer data to and from the Control Register pointed at by the EIR register. 4.5.15 ECP Extended Auxiliary Status Register (EAR) Upon reset, this register is initialized to 00h. Bits 6-0 - Reserved Bit 7 - FIFO Tag Read only. In mode 011, when bit 5 of the DCR is 1 (backward direction), this bit reflects the value of the tag bit (BUSY status) of the word currently in the bottom of the FIFO. In other modes this bit is indeterminate. 4.5.16 Control0 Register Upon reset, this register is initialized to 00h. Bit 0 - EPP Time-Out Interrupt Mask 0: The EPP time-out is masked. 1: The EPP time-out is generated. Bit 3-1 - Reserved Bit 4 - Freeze Bit In mode 011, setting this bit to 1 freezes part of the in- terface with the peripheral device, and clearing this bit to 0 releases and initializes it. In all other modes the value of this bit is ignored. Bit 5 - DCR Register Live When this bit is 1, reading DCR (see Section 4.5.6 "ECP Control Register (DCR)" on page 89) reads the interface control lines pin values regardless of the mode selected. Otherwise, reading the DCR reads the content of the register. Bits 7, 6 - Reserved 4.5.17 Control2 Register Upon reset, this register is initialized to 00h. Bits 3-0 - Reserved Bit 4 - EPP 1.7/1.9 Select Selects EPP version 1.7 or 1.9. 0: EPP version 1.7. 1: EPP version 1.9. 76543210 Reset Required 0 0 0 0 0 0 0 0 ECP Extended Data Register (EDR) Offset 404h Data Bits D2 D4 D5 D6 D7 D0 D1 D3 76543210 Reset Required 0 0 0 0 0 0 0 0 ECP Extended Auxiliary Offset 405h Reserved FIFO Tag Status Register (EAR) 76543210 Reset Required 0 0 0 0 0 0 0 0 Control0 Register Offset 00h Reserved EPP Time-Out Reserved Reserved Reserved Reserved Freeze Bit DCR Register Live Second Level Interrupt Mask 76543210 Reset Required 0 0 0 0 0 0 0 0 Control2 Register Offset 02h Revision 1.7 or 1.9 Select Channel Address Enable Reserved Reserved SPP Compatability Second Level |
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