PC87309VLJ datasheet(86/192 Pages) NSC

86 / 192 page

Parallel Port (Logical Device 1)

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FIGURE 4-3. EPP 1.9 Address Write

EPP 1.9 Address Read

The following procedure reads from the address register.

1. The system reads a byte from the EPP address register.

When RD becomes low, the EPP pulls IOCHRDY low,

and waits for WAIT to become low.

2. When WAIT becomes low, the EPP pulls ASTRB low

and waits for WAIT to become high. If WAIT was already

low, steps 2 and 3 occur concurrently.

3. When WAIT becomes high, the EPP stops pulling IO-

CHRDY low, and waits for RD to become high.

4. When RD becomes high, the EPP latches PD7-0 (to

provide sufficient hold time), pulls ASTRB high, and puts

D7-0 in TRI-STATE.

FIGURE 4-4. EPP 1.9 Address Read

EPP 1.9 Data Write and (Backward) Data Read

This procedure writes to the selected peripheral drive or

EPP 1.9 data read and write operations are similar to EPP

1.9 address read and write operations, except that the data

strobe (DSTRB signal) and EPP Data register replace the

address strobe (ASTRB signal) and the EPP Address reg-

ister, respectively.

4.4

EXTENDED CAPABILITIES PARALLEL PORT

(ECP)

In the Extended Capabilities Parallel Port (ECP) modes, the

device is a state machine that supports a 16-byte FIFO that

can be configured for either direction, command and data

FIFO tags (one per byte), a FIFO threshold interrupt for both

directions, FIFO empty and full status bits, automatic gen-

eration of strobes (by hardware) to fill or empty the FIFO,

transfer of commands and data, and Run Length Encoding

(RLE) expanding (decompression) as explained below. The

FIFO can be accessed by PIO or system DMA cycles.

4.4.1

ECP Modes

ECP modes are enabled as described in TABLE 4-1 "Par-

allel Port Mode Selection" on page 80. The ECP mode is se-

lected at reset by setting bits 7-5 of the SuperI/O Parallel

Port Configuration register at index F0h (see Section 2.6

"SUPERI/O PARALLEL PORT CONFIGURATION REGIS-

TER (LOGICAL DEVICE 1)" on page 30) to 100 or 111.

Thereafter, the mode is controlled via the bits 7-5 of the

ECP Extended Control Register (ECR) at offset 402h of the

parallel port. See Section 4.5.12 "Extended Control Regis-

ter (ECR)" on page 91.

TABLE 4-9 "ECP Modes Encoding" on page 92 lists the

ECP modes. See TABLE 4-11 "ECP Modes" on page 96

and Section 4.6 "DETAILED ECP MODE DESCRIPTIONS"

on page 95 for more detailed descriptions of these modes.

4.4.2

Software Operation

Software should operate as described in “

Extended Capa-

bilities Port Protocol and ISA Interface Standard”.

Some of these operations are:

Software should enable ECP after bits 3-0 of the parallel

port Control Register (CTR) are set to 0100.

When ECP is enabled, software should switch modes

only through modes 000 or 001.

When ECP is enabled, the software should change di-

rection only in mode 001.

Software should not switch from mode 010 or 011, to

mode 000 or 001, unless the FIFO is empty.

Software should switch to mode 011 when bits 0 and 1

of DCR are 0.

Software should switch to mode 010 when bit 0 of DCR

is 0.

Software should disable ECP only in mode 000 or 001.

Software should switch to mode 100 when bits 0, 1 and

3 of the DCR are 0.

Software should switch from mode 100 to mode 000 or

001 only when bit 7 of the DSR (BUSY) is 1. Otherwise,

an on-going EPP cycle can be aborted.

When the ECP is in mode 100, software should write 0

to bit 5 of the DCR before performing EPP cycles.

Software may switch from mode 011 backward to modes

000 or 001, when there is an on-going ECP read cycle. In

this case, the read cycle is aborted by deasserting AFD.

The FIFO is reset (empty) and a potential byte expansion

(RLE) is automatically terminated since the new mode is

000 or 001.

D7-0

WAIT

ASTRB

WRITE

PD7-0

IOCHRDY

D7-0

WAIT

ASTRB

WRITE

PD7-0

IOCHRDY

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