PC87309VLJ datasheet(81/192 Pages) NSC

81 / 192 page

Parallel Port (Logical Device 1)

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If bit 5 of CTR is cleared to 0, data is written to the output

signals PD7-0 when a write cycle occurs. (if a read cycle oc-

curs in this setting, the system reads the output latch, not

data from PD7-0).

If bit 5 of CTR is set to 1, data is read from the output signals

PD7-0 when a read cycle occurs. A write cycle in this setting

only writes to the output latch, not to the output signals PD7-

The reset value of this register is 0.

4.2.3

Status Register (STR)

This read-only register holds status information. A system

write operation to STR is an invalid operation that has no ef-

fect on the parallel port.

Bit 0 - Time-Out Status

In EPP modes only, this is the time-out status bit. In all

other modes this bit has no function and has the con-

stant value 1.

This bit is cleared when an EPP mode is enabled.

Thereafter, this bit is set to 1 when a time-out occurs in

an EPP cycle and is cleared when STR is read.

In EPP modes:

0: An EPP mode is set. No time-out occurred since

STR was last read.

1: Time-out occurred on EPP cycle (minimum of 10

µsec). (Default)

Bit 1 - Reserved

This bit is reserved and is always 1.

Bit 2 - IRQ Status

In all modes except SPP Extended, this bit is always 1.

In SPP Extended mode this bit is the IRQ status bit. It re-

mains high unless the interrupt request is enabled (bit 4 of

CTR set high). This bit is high except when latched low

when the ACK signal makes a low to high transition, indi-

cating a character is now being transferred to the printer.

Reading this bit resets it to 1.

0: Interrupt requested in SPP Extended mode.

1: No interrupt requested. (Default)

Bit 3 - ERR Status

This bit reflects the current state of the printer error sig-

nal, ERR. The printer sets this bit low when there is a

printer error.

0: Printer error.

1: No printer error.

Bit 4 - SLCT Status

This bit reflects the current state of the printer select sig-

nal, SLCT. The printer sets this bit high when it is on-line

and selected.

0: No printer selected.

1: Printer selected and online.

Bit 5 - PE Status

This bit reflects the current state of the printer paper end

signal (PE). The printer sets this bit high when it detects

the end of the paper.

0: Printer has paper.

1: End of paper in printer.

Bit 6 - ACK Status

This bit reflects the current state of the printer acknowl-

edge signal, ACK. The printer pulses this signal low af-

ter it has received a character and is ready to receive

another one. This bit follows the state of the ACK pin.

0: Character reception complete.

1: No character received.

Bit 7 - Printer Status

This bit reflects the current state of the printer BUSY sig-

nal. The printer sets this bit low when it is busy and can-

not accept another character.

This bit is the inverse of the (BUSY/WAIT) pin.

0: Printer busy.

1: Printer not busy.

4.2.4

SPP Control Register (CTR)

The control register provides all the output signals that con-

trol the printer. Except for bit 5, it is a read and write register.

Normally when the Control Register (CTR) is read, the bit

values are provided by the internal output data latch. These

bit values can be superseded by the logic level of the STB,

AFD, INIT, and SLIN signals, if these signals are forced high

or low by external voltage. To force these signals high or

low the corresponding bits should be set to their inactive

states (e.g., AFD, STB and SLIN should all be 0; INIT

should be 1).

76543210

Reset

Required

SPP Data Register

(DTR)

Offset 00h

Data Bits

76543210

Reset

Required

SPP Status Register

(STR)

Offset 01h

IRQ Status

SLCT Status

PE Status

ACK Status

Printer Status

Time-Out Status

Reserved

ERR Status

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