PC87309VLJ datasheet(60/192 Pages) NSC

60 / 192 page

The Floppy Disk Controller (FDC) (Logical Device 0)

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3.7.6

The LOCK Command

The LOCK command can be used to keep the FIFO en-

abled and to retain the values of some parameters after a

software reset.

After the command byte of the LOCK command is written,

its result byte must be read before the opcode of the next

command can be read. The LOCK command is not execut-

ed until its result byte is read by the microprocessor.

If the part is reset after the command byte of the LOCK com-

mand is written but before its result byte is read, then the

LOCK command is not executed. This prevents accidental

execution of the LOCK command.

Command Phase

Bit 7 - Control Reset Effect (LOCK)

This bit determines how the FIFO, THRESH, and

PRETRK bits in the CONFIGURE command and, the

FWR, FRD, and BST bits in the MODE command are af-

fected by a software reset.

0: Set default values after a software reset. (Default)

1: Values are unaffected by a software reset.

Execution Phase

Internal register is written.

Result Phase

Bit 4 - Control Reset Effect (LOCK)

Same as bit 7 of opcode in command phase.

3.7.7

The MODE Command

This command selects the special features of the controller.

The bits in the command bytes of the MODE command are

set to their default values after a hardware reset.

Command Phase

Second Command Phase Byte

Bit 0 - Extended Track Range (ETR)

This bit determines how the track number is stored. It is

cleared to 0 after a software reset.

0: Track number is stored as a standard 8-bit value

compatible with the IBM, ISO, and Toshiba Perpen-

dicular formats.

This allows access of up to 256 tracks during a

seek operation. (Default)

1: Track number is stored as a 12-bit value.

The upper four bits of the track value are stored in

the upper four bits of the head number in the sector

address ﬁeld.

This allows access of up to 4096 tracks during a

seek operation. With this bit set, an extra byte is re-

quired in the SEEK command phase and SENSE

INTERRUPT result phase.

Bits 3,2 - Low-Power Mode (LOW PWR)

These bits determine whether or not the FDC powers

down and, if it does, they specific how long it will take.

These bits disable power down, i.e., are cleared to 0, af-

ter a software reset.

00: Disables power down. (Default)

01: Automatic power down.

At a 500 Kbps data transfer rate, the FDC goes into

low-power mode 512 msec after it becomes idle.

At a 250 Kbps data transfer rate, the FDC goes into

low-power mode 1 second after it becomes idle.

10: Manual power down.

The FDC powers down mode immediately.

11: Not used.

Bit 5 - Implied Seek (IPS)

This bit determines whether the Implied Seek (IPS) bit

in a command phase byte of a read, write, scan, or verify

command is ignored or READ.

A software reset clears this bit to its default value of 0.

0: The IPS bit in the command byte of a read, write,

scan, or verify is ignored. (Default)

Implied seeks can still be enabled by the Enable

Implied Seeks (EIS) bit (bit 6 of the third command

phase byte) in the CONFIGURE command.

1: The IPS bit in the command byte of a read, write,

scan, or verify is read.

If it is set to 1, the controller performs seek and

sense interrupt operations before executing the

command.

Bit 6 - Index Address Format (IAF)

This bit determines whether the controller formats

tracks with or without an index address field.

A software reset clears this bit to its default value of 0.

0: The controller formats tracks with an index address

ﬁeld. (IBM and Toshiba Perpendicular format).

1: The controller formats tracks without an index ad-

dress ﬁeld. (ISO format).

Bit 7 - Motor Timer Values (TMR)

This bit determines which group of values to use to cal-

culate the Delay Before Processing and Delay After Pro-

cessing times. The value of each is programmed using

the SPECIFY command, which is described in TABLES

3-23 on page 74 and 3-24 on page 74.

A software reset clears this bit to its default value of 0.

76543210

LOCK

0010100

76543210

LOCK

0000

76543210

00000001

TMR

IAF

IPS

LOW PWR

ETR

FWR

FRD

BST

R255

0000

DENSEL

BFR

WLD

Head Settle Factor

00000000

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