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ADC32RF83 データシート(PDF) 111 Page - Texas Instruments |
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ADC32RF83 データシート(HTML) 111 Page - Texas Instruments |
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111 / 138 page  111 ADC32RF80, ADC32RF83 www.ti.com SBAS774A – MAY 2016 – REVISED DECEMBER 2016 Product Folder Links: ADC32RF80 ADC32RF83 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated 8.5.13.5 Register 00Bh-00Ch (address = 00Bh-00Ch), Power Detector Page Figure 223. Register 00Bh 7 6 5 4 3 2 1 0 DWELL[7:0] R/W-0h LEGEND: R/W = Read/Write; -n = value after reset Figure 224. Register 00Ch 7 6 5 4 3 2 1 0 DWELL[15:8] R/W-0h LEGEND: R/W = Read/Write; -n = value after reset Table 102. Register 00Bh-00Ch Field Descriptions Bit Field Type Reset Description 7-0 DWELL R/W 0h DWELL time counter. When the computed block peak crosses the upper thresholds BLKTHHH or BLKTHLH, the peak detector output flags are set. In order to be reset, the computed block peak must remain continuously lower than the lower threshold (BLKTHHL or BLKTHLL) for the period specified by the DWELL value. This threshold is 16 bits, is specified in terms of fS / 8 clock cycles, and must be set to 0 for the crossing detector. Example: if fS = 3 GSPS, fS / 8 = 375 MHz, and DWELL = 0100h then the DWELL time = 29 / 375 MHz = 1.36 µs. 8.5.13.6 Register 00Dh (address = 00Dh), Power Detector Page Figure 225. Register 00Dh 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 FILT0LPSEL W-0h W-0h W-0h W-0h W-0h W-0h W-0h R/W-0h LEGEND: R/W = Read/Write; W = Write only; -n = value after reset Table 103. Register 00Dh Field Descriptions Bit Field Type Reset Description 7-1 0 W 0h Must write 0 0 FILT0LPSEL R/W 0h This bit selects either the block detector output or 2-bit output as the input to the IIR filter. 0 = Use the output of the high comparators (HH and HL) as the input of the IIR filter 1 = Combine the output of the high (HH and HL) and low (LH and LL) comparators to generate a 3-level input to the IIR filter (–1, 0, 1) |
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