R34DS0017EU0104 Rev.1.04

Page 31

Jan 31, 2025

ISL73041SEH Datasheet

The dynamic current from the duty cycle is because of the 500Ω pull-down resistor on LGL and 1kΩ resistor on

UGL. During one switching cycle, the current through these resistors is Equation 7, where R1 is 1kΩ, R2 is 500Ω,

and D is the duty cycle of the gate drive waveform.

6.17 Power Dissipation

The power dissipation calculation for the ISL73041SEH half-bridge driver is more complex compared to typical

half-bridge drivers where most of the power is dissipated by the dynamic operating current of the driver and in the

output driver stage switching the capacitive load of the FET gates. While the dynamic current and output drive

dissipation are still significant portions, the ISL73041SEH total power dissipation must also include the two

internal LDOs, the current to bias the RDU and RDL dead time circuits, and the internal 1kΩ pull-down resistor on

the upper gate driver and the 500Ω pull-down resistor on the lower gate driver as these attributes further increase

the power dissipation. Therefore, VDD biasing voltage, PVCC LDO regulated voltage, programmed dead time,

and even duty cycle operation become factors in the total power dissipation. Use the spreadsheet calculator tool

on the product page to estimate the total power dissipation in the ISL73041SEH driver.

6.18 Dual Complimentary Low-Side GaN FET Driver

The ISL73041SEH can be configured as a dual complementary output low-side driver controlled by the PWM

input. Such an application can be used in synchronous low-side drives of transformer-isolated topologies.

Connect the PHS pin common to PGND to ground the upper driver. Connect the BOOT pin to the PVCC pin to

bypass the boot switch. The upper driver UG is in phase with the PWM input, while the lower driver LG is logically

inverted from PWM. The dead time from UG falling to LG rising and LG falling to UG rising is still enforced by the

dead time resistors on RDU and RDL in this configuration. Either GaN FET may be omitted in this configuration to

use the ISL73041SEH as a single inverting (LG only) or non-inverting (UG only) GaN FET Driver.

(EQ. 7)

I_VDD duty cycle



PVCC

R1

----------------- D PVCC

R2

-----------------

1D

–





+



=