R34DS0017EU0104 Rev.1.04

Page 4

Jan 31, 2025

ISL73041SEH Datasheet

2.

Pin Information

2.1

Pin Assignments

2.2

Pin Descriptions

Figure 3. Pin Assignments - Top View

Note: The package lid is branded with a triangular mark that is placed near Pin #1. The Pin #1 bottom pad is approximately twice as

long as Pin #2 through #16. The lid seal ring flashing is extended around the castellation of Pin #1 for a visual indicator.

Pin

Number

Pin Name

ESD

Circuit

Description

1EN

2

Enable input pin. When EN is low, driver outputs are in a high-impedance state and do not

respond to PWM inputs. The PVCC LDO is shut down, and the FLT pin is internally pulled

low. When EN is high, the PVCC LDO is enabled, and the driver outputs respond to PWM

inputs. EN pin is VDD voltage compliant.

2PWM

1

Tri-Level PWM input pin. Logic high turns on the high-side gate driver. Logic low turns on the

low-side gate driver. Mid-Level turns off both gate drivers. Internal pull-up and pull-down

resistors bias pin to mid-level when not externally driven.

3FLT

1

I/O pin. As an open-drain output, FLT is an active low indicator for when EN = 0, VDD UVLO,

AVCC UVLO, PVCC UVLO, or in an over-temperature fault. As a high-impedance input, FLT

disables the driver outputs when driven low. Place a pull-up resistor on the FLT pin to AVCC.

Place a 10pF capacitor from FLT to GND for SET mitigation.

4RDU

1

Dead time delay control for the high-side turn-on. A 1.3kΩ-10kΩ resistor to SGND sets the

rising edge delay of Upper Gate High (UGH) to the falling edge of Lower Gate Low (LGL) in

the range of 6.5ns to 50ns.

5RDL

1

Dead time delay control for low-side turn-on. A 1.3kΩ-10kΩ resistor to SGND sets the rising

edge delay of Lower Gate High (LGH) to the falling edge of Upper Gate Low (UGL) in the

range of 6.5ns-50ns.

3

4

5

6

14

13

12

11

RDU

RDL

AVCC

LGL

LGH

PHS

UGL

FLT