R34DS0017EU0104 Rev.1.04

Page 14

Jan 31, 2025

ISL73041SEH Datasheet

LG Fall Time

tLGF

VDD = 4.75V;

PVCC = BOOT-PHS = 4.5V

LG CLOAD = 10nF; 90% to 10%

-55 to

+125°C

--

30

ns

VDD = 4.75V;

PVCC = BOOT-PHS = 4.5V

LG CLOAD = 940nF; 70% to 30%

-55°C

160

240

340

+25°C

220

270

380

+125°C

260

350

420

+25°C

(Post Rad)

160

280

420

Mode Transition Delay

PVCC Start-Up Delay

-

VDD = 4.75V; PVCC = FB;

CPVCC = 1.0µF;

EN High to PVCC crossing 0.5V

--

115

-

µs

PVCC Start-Up Time

-

VDD = 4.75V; PVCC = FB;

CPVCC = 1.0µF;

PVCC rise time from 0.45V to 4.05V

(10% to 90% of 4.5V)

--

15

-

µs

EN High to Driver Output

Enabled Delay Time

tENR

VDD = PVCC = FB = BOOT-PHS = 4.75V

-55 to

+125°C

70

95

130

µs

EN Low to Driver Output

Disabled Delay Time

tENF

EN Low to UG Off; PWM = 5V

EN Low to LG Off; PWM = 0V

-4

8

µs

FLT Low to LG Output

Falling

tFLTF

VDD = 4.75V;

PVCC = BOOT-PHS = 4.5V; EN = VDD;

PWM = 0V; FLT exercised as an input pin

High to Low

-

200

300

ns

FLT High to LG Output

Rising

tFLTR

VDD = 4.75V;

PVCC = BOOT-PHS = 4.5V; EN = VDD;

PWM = 0V; FLT exercised as an input pin

Low to High

-

300

400

ns

PVCC Falling Below

UVLO to FLT Falling

Delay

tPVCCF

FB = PVCC

-

-

0.6

-

µs

PVCC Falling Below

UVLO to UG Falling

Delay

FB = PVCC; PWM = 5V

-

-

0.8

-

µs

PVCC Falling Below

UVLO to LG Falling

Delay

FB = PVCC; PWM = 0V

-

-

0.5

-

µs

Unless otherwise specified: VDD = 13.2V; EN = VDD; PVCC = 5.5V; CPVCC = 2.2µF; CAVCC = 2.2µF; CBOOT = 100nF to PHS;

PHS = PGND = 0V, TA=25°C. UG is defined as UGH = UGL. LG is defined as LGH = LGL. Boldface specifications apply across

the operating temperature range from TA= -55°C to +125°C and across a total ionizing dose of 75krad(Si) at +25°C with

exposure at a low dose rate of <10mrad(Si)/s.

Parameter

Symbol

Test Conditions

Temp.

Min[1]

Typ[2]

Max[1]

Unit