H8SXSLASH1663M datasheet(514/1504 Pages) RENESAS

514 / 1504 page

Section 11 EXDMA Controller (EXDMAC)

Rev. 2.00 Sep. 24, 2008 Page 482 of 1468

REJ09B0412-0200

11.5

Mode Operation

11.5.1

Address Modes

(1)

Dual Address Mode

In dual address mode, the transfer source address is set in EDSAR, and the transfer destination

address is set in EDDAR. One transfer operation is executed in two bus cycles. (When the data

bus width is smaller than the data access size or when the address to be accessed is not at the data

boundary of the data access size, the bus cycle is divided, resulting more than two bus cycles.)

In a transfer operation, the data on the transfer source address is read in the first bus cycle, and is

written to the transfer destination address in the next bus cycle.

These consecutive read and write cycles are indivisible: another bus cycle (external access by

another bus master, refresh cycle, or external bus release cycle) does not occur between these two

cycles.

ETEND pin output can be enabled or disabled by means of the ETENDE bit in EDMDR. ETEND

is output for two consecutive bus cycles. When an idle cycle is inserted before the bus cycle, the

ETEND signal is also output in the idle cycle. The EDACK signal is not output.

Figure 11.2 shows an example of the timing in dual address mode and figure 11.3 shows the dual

address mode operation.

Address bus

ETEND

EXDMA read

cycle

EXDMA write

cycle

EDSAR

EDDAR

Figure 11.2 Example of Timing in Dual Address Mode

H8SX/1663M データシート(PDF) 514 Page - Renesas Technology Corp