H8SXSLASH1663M datasheet(802/1504 Pages) RENESAS

部品番号	H8SX/1663M

部品情報	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

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802 / 1504 page

Section 14 16-Bit Timer Pulse Unit (TPU)

Rev. 2.00 Sep. 24, 2008 Page 770 of 1468

REJ09B0412-0200

14.10.7

Conflict between Buffer Register Write and Compare Match

If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the

buffer operation will be the write data.

Figure 14.50 shows the timing in this case.

TGR

Compare match

signal

Address

Write

TGR write cycle

Buffer register

address

Data written to buffer register

Buffer register

Figure 14.50 Conflict between Buffer Register Write and Compare Match

14.10.8

Conflict between TGR Read and Input Capture

If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read

will be the data after input capture transfer.

Figure 14.51 shows the timing in this case.

TGR

Input capture

signal

Address

TGR address

Read

TGR read cycle

Internal data

bus

Figure 14.51 Conflict between TGR Read and Input Capture

H8SX/1663M データシート(PDF) 802 Page - Renesas Technology Corp

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