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H8SX/1663M データシート(PDF) 316 Page - Renesas Technology Corp

部品番号 H8SX/1663M
部品情報  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663M データシート(HTML) 316 Page - Renesas Technology Corp

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Section 9 Bus Controller (BSC)
Rev. 2.00 Sep. 24, 2008 Page 284 of 1468
REJ09B0412-0200
9.10.7
Controlling Row Address Output Cycle
The
RAS signal is driven low at the start of the Tr cycle by setting the RAST bit to 1. The row
address hold time to the falling edge of the
RAS signal and the DRAM read access time are
changed. Set the bit according to the DRAM to be used and the frequency of this LSI so that
required performance can be obtained.
Figure 9.40 shows a timing example when the
RAS signal is driven low at the start of the Tr cycle.
T
p
T
r
T
c1
T
c2
Address bus
Row address
Column address
B
φ
RAS
LUCAS
LLCAS
WE
OE (RD)
WE
OE (RD)
Data bus
High
High
Read
Write
Data bus
BS
RD/
WR
Figure 9.40 Access Timing Example of
RAS Signal Driven Low at Start of Tr Cycle
(CAST = 0)



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