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MEC1322 データシート(PDF) 61 Page - Microchip Technology |
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MEC1322 データシート(HTML) 61 Page - Microchip Technology |
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61 / 456 page  2014 - 2015 Microchip Technology Inc. DS00001719D-page 61 MEC1322 Note 3-12 This is the latency following a wake event until the 48 MHz Ring Oscillator is locked and clocking the system. 3.9.8 PROCESSOR CLOCK CONTROL REGISTER (PROC_CLK_CNTRL) 3.9.9 EC SLEEP ENABLE 2 REGISTER (EC_SLP_EN2) TABLE 3-10: SYSTEM SLEEP CONTROL BIT ENCODING D2 D1 D0 Wake Latency (TYP) Description 0 0 0 0 The Core regulator and the Ring Oscillator remain powered and run- ning during sleep cycles (SYSTEM HEAVY SLEEP 1) (DEFAULT) 0 1 0 0 The Core regulator remains powered and the Ring oscillator is running but gated during sleep cycles (SYSTEM HEAVY SLEEP 2) 0 X 1 200us (Note 3-12) The Core regulator remains powered and the Ring oscillator is powered down during sleep cycles (SYSTEM HEAVY SLEEP 3) 1 X 1 1ms The Core regulator is suspended and the Ring oscillator is powered down during sleep cycles. (SYSTEM DEEPEST SLEEP) Offset 20h Bits Description Type Default Reset Event 31:8 RESERVED RES 7:0 Processor Clock Divide Value 1: divide 48 MHz Ring Oscillator by 1. 4: divide 48 MHz Ring Oscillator by 4. 16: divide 48 MHz Ring Oscillator by 16. 48: divide 48 MHz Ring Oscillator by 48. No other values are supported. R/W 4h VCC1_R ESET Offset 24h Bits Description Type Default Reset Event 31:29 RESERVED RES 28 MCHP Reserved (Note 3-10)R/W 0h VCC1_R ESET 27 MCHP Reserved (Note 3-10)R/W 0h VCC1_R ESET 26 MCHP Reserved (Note 3-10)R/W 0h VCC1_R ESET 25 LED3 Sleep Enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. R/W 0h VCC1_R ESET 24 TIMER32_1 Sleep Enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. See Note 3-11 on page 57. R/W 0h VCC1_R ESET 23 TIMER32_0 Sleep Enable 0: block is free to use clocks as necessary. 1: block is commanded to sleep at next available moment. See Note 3-11 on page 57. R/W 0h VCC1_R ESET |
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