MEC1322 datasheet(78/456 Pages) MICROCHIP

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MEC1322

DS00001719D-page 78

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Note 5-1

The EC can determine the state of the LRESET# input using registers in LPC Bus Monitor Register

on page 95.

Note 5-2

VCC1_RESET is asserted when VCC1 is turned off and is released after VCC1 is turned on. The

VCC1_RESET will be released before the System Host is expected to attempt communication over

the LPC Interface.

Note 5-3

See the individual register descriptions to determine which registers are effected by nSIO_RESET.

Note 5-4

The LPC Interface will be ready to receive a new transaction when LRESET# is deasserted. See the

individual register descriptions to determine which registers are effected by this reset.

In system, the LPC Interface is required to be operational in ACPI Sleep States S0 - S2. When the system enters Sleep

States S3 - S5 the LPC interface must tristate its outputs. The following table shows the behavior of LPC output and

input/output signals under reset conditions.

5.6

Interrupts

This section defines the Interrupt Sources generated from this block.

5.7

Low Power Modes

The LPC Controller may be put into a low power state by the chip’s Power, Clocks, and Reset (PCR) circuitry.

The LPC Block has implemented an EC Clock Control Register to determine how the internal clocks are effected by the

supported low power modes. See Section 5.11.4, "EC Clock Control Register," on page 96 for a description of these

options.

5.8

Description

This LPC Controller is compliant with the Intel® Low Pin Count (LPC) Interface Specification, v1.1. Section 5.8.1, "LPC

Controller Description" further clarifies which LPC Interface features have been implemented and qualifies any system

specific requirements.

TABLE 5-6:

LPC Interface BLOCK RESET STATES

VCC1_RESET

(Note 5-2)

LRESET#

(Note 5-1, Note 5-4)

nSIO_RESET

(Note 5-3)

Reset State

Asserted

Resets all registers and logic

Deasserted

Asserted

Resets selected registers and logic

Deasserted

Asserted

Resets selected registers

Deasserted

Nothing is in Reset

Note:

See Section 5.8.1.3, "LPC Clock Run," on page 80 page 157 for LPC protocol dependent pin state transi-

tions requirements.

TABLE 5-7:

LPC INTERFACE SIGNALS BEHAVIOR ON RESET

Pins

VCC1_RESET

nSIO_RESET

LRESET#

Asserted

LAD[3:0]

Tri-state

Tri-State

SERIRQ

Tri-state

Tri-State

CLKRUN#

Tri-state

Tri-State

Source

Description

LPC_INTERNAL_ERR

The LPC_INTERNAL_ERR event is sourced by bit D0 of the Host Bus

Error Register.

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