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MEC1322 データシート(PDF) 90 Page - Microchip Technology |
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MEC1322 データシート(HTML) 90 Page - Microchip Technology |
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90 / 456 page  MEC1322 DS00001719D-page 90 2014 - 2015 Microchip Technology Inc. 5.9.2.1 SIRQ Configuration Register Format Note 5-9 See Table 5-15, “SIRQ Interrupt Configuration Register Map,” on page 90. 5.9.2.2 SIRQ Configuration Registers Offset See Table 5-15, “SIRQ Interrupt Configuration Register Map,” on page 90. Bits Description Type Default Reset Event 7 SELECT If this bit is 1, the first interrupt signal from the Logical Device is selected for the SERIRQ vector. If this bit is 0, the second interrupt signal from the Logical Device is selected. Note: The Keyboard Controller is an example of a Logical Devices that requires a second interrupt signal. Most Logical Devices require only a single interrupt and ignore this field as result. R/W Note 5-9 nSIO_R ESET 6 DEVICE This field should always be set to 0 in order to enable a SERIRQ. R/W Note 5-9 nSIO_R ESET 5:0 FRAME These six bits select the Logical Device for on-chip devices as the source for the interrupt. Note: The LPC Logical Device (Logical Device Number 0Ch) can be used by the Embedded Controller to generate a Serial Interrupt Request to the Host under software con- trol. R/W Note 5-9 nSIO_R ESET TABLE 5-15: SIRQ INTERRUPT CONFIGURATION REGISTER MAP Offset Type Reset Configuration Register Name 40h R/W FFh IRQ0 41h R/W FFh IRQ1 42h R/W FFh IRQ2 43h R/W FFh IRQ3 44h R/W FFh IRQ4 45h R/W FFh IRQ5 46h R/W FFh IRQ6 47h R/W FFh IRQ7 48h R/W FFh IRQ8 49h R/W FFh IRQ9 4Ah R/W FFh IRQ10 4Bh R/W FFh IRQ11 4Ch R/W FFh IRQ12 4Dh R/W FFh IRQ13 4Eh R/W FFh IRQ14 4Fh R/W FFh IRQ15 Note: A SERIRQ interrupt is deactivated by setting an entry in the SIRQ Interrupt Configuration Register Map to FFh, which is the default reset value. |
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