MEC1322 datasheet(66/456 Pages) MICROCHIP

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MEC1322

DS00001719D-page 66

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3.9.13

PCR CHIP SUB-SYSTEM POWER RESET STATUS (CHIP_PWR_RST_STS)

Note 3-15

This read-only status bit always reflects the current status of the event and is not affected by any

Reset events.

Offset

34h

Bits

Description

Type

Default

Reset

Event

31:12 RESERVED

RES

11 PCICLK_ACTIVE

This bit monitors the state of the PCI clock input. This status bit

detects edges on the clock input but does not validate the frequency.

0: The 33MHz PCI clock input is not present.

1: The 33MHz PCI clock is present.

R-

VCC1_R

ESET

10 32K_ACTIVE

This bit monitors the state of the 32K clock input. This status bit

detects edges on the clock input but does not validate the frequency.

0: The 32K clock input is not present. The internal 32K clock is

derived from the ring oscillator

1: The 32K clock input is present. The internal 32K clock is derived

from the pin and the ring oscillator is synchronized to the external

32K clock.

R-

VCC1_R

ESET

9:7 RESERVED

RES

6 VCC1 reset status

Indicates the status of VCC1_RESET.

0 = No reset occurred since the last time this bit was cleared.

1 = A reset occurred.

Note:

The bit will not clear if a write 1 is attempted at the same

time that a VCC1_RST_N occurs, this way a reset event

is never missed.

R/WC

VCC1_R

ESET

5 VBAT reset status

Indicates the status of VBAT_POR.

0 = No reset occurred while VCC1 was off or since the last time this

bit was cleared.

1 = A reset occurred.

Note:

The bit will not clear if a write 1 is attempted at the same

time that a VBAT_RST_N occurs, this way a reset event

is never missed.

R/WC

VCC1_R

ESET

4 RESERVED

RES

3 SIO_Reset Status

Indicates the status of nSIO_RESET.

0 = reset active.

1 = reset not active.

Rxh

Note 3-

2 VCC Reset Status

Indicates the status of PWRGD.

0 = reset active (PWRGD not asserted).

1 = reset not active (PWRGD asserted).

Rxh

Note 3-

1:0 RESERVED

RES

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