PC87309VLJ datasheet(124/192 Pages) NSC

124 / 192 page

Enhanced Serial Port with IR -UART2 (Logical Device 2)

124

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5.16.1

Reserved Registers

Bank 5 registers with offsets 00h-02h are reserved.

5.16.2

(LCR/BSR) Register

These registers are the same as the registers at offset 03h

in bank 0.

5.16.3

Infrared Control Register 2 (IRCR2)

This register controls the basic settings of the infrared

modes.

Upon reset, the content of this register is 02h.

Bit 0 - Enable Infrared Full Duplex Mode (IR_FDPLX)

When set to 1, the infrared receiver is not masked dur-

ing transmission.

Bit 1 - MSR Register Function Select in Infrared Mode

(IRMSSL)

This bit selects the behavior of the Modem Status Reg-

ister (MSR) and the Modem Status Interrupt (MS_EV)

when any infrared mode is selected. When a UART

mode is selected, the Modem Status Register and the

Modem Status Interrupt function normally, and this bit is

ignored.

0: MSR register and modem status interrupt work in

the IR modes as in the UART mode (Enables exter-

nal circuitry to perform carrier detection and pro-

vide wake-up events).

1: The MSR returns 30h, and the Modem Status In-

terrupt is disabled. (Default)

Bits 3,2 -Reserved

Read/Write 0.

Bit 4 - Auxiliary Infrared Input Select (AUX_IRRX)

When set to 1, the infrared signal is received from the

auxiliary input. (Separate input signals may be desired

for different front-end circuits). See Table 5-29 on page

130.

Bit 5-7 - Reserved

Read/Write 0.

5.16.4

Reserved Registers

Bank 5 registers with offsets 05h-07h are reserved.

5.17 BANK 6 – INFRARED PHYSICAL LAYER

CONFIGURATION REGISTERS

This Bank of registers controls aspects of the framing and

timing of the infrared modes.

TABLE 5-21. Bank 6 Register Set

5.17.1

Infrared Control Register 3 (IRCR3)

This register enables/disables modulation in Sharp-IR

mode.

Upon reset, the content of this register is 20h.

Bit 0-5 - Reserved

Read/Write 0.

Bit 6 - Sharp-IR Modulation Disable (SHMD_DS)

0: Enables internal 500 KHz transmitter modulation.

(Default)

1: Disables internal modulation.

Bit 7 - Sharp-IR Demodulation Disable (SHDM_DS)

0: Enables internal 500 KHz receiver demodulation.

(Default)

1: Disables internal demodulation.

5.17.2

Reserved Register

Bank 6 register with offset 01h is reserved.

5.17.3

SIR Pulse Width Register (SIR_PW)

This register sets the pulse width for transmitted pulses in

SIR operation mode. These setting do not affect the receiv-

er. Upon reset, the content of this register is 00h, which de-

faults to a pulse width of 3/16 of the baud.

76543210

Reset

Required

(IRCR2)

Bank 5,

AUX_IRRX

IR_FDPLX

IRMSSL

Infrared Control

Offset 04h

Reserved

Offset

Name

Description

00h

IRCR3

Infrared Control Register 3

01h

Reserved

02h

SIR_PW

SIR Pulse Width Control

(

≤ 115 Kbps)

03h

LCR/ BSR

Link Control Register/

Bank Select Register

04h - 07h

Reserved

76543210

Reset

Required

(IRCR3)

Bank 6,

Infrared Control

SHMD_DS

SHDM_DS

Offset 00h

Reserved

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