PC87309VLJ datasheet(121/192 Pages) NSC

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Enhanced Serial Port with IR -UART2 (Logical Device 2)

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Bit 6 - Reserved

Write 1.

Bit 7 - Baud Generator Test (BTEST)

When set to 1, this bit routes the Baud Generator output

to the DTR pin for testing purposes.

5.13.3

Link Control Register (LCR) and Bank Select

These registers are the same as the registers at offset 03h

in bank 0.

5.13.4

Extended Control and Status Register 2

(EXCR2)

This register configures the Prescaler and controls the

Baud Divisor Register Lock.

Upon reset all bits are set to 0.

Bits 3 - 0 - Reserved

Read/Write 0.

Bits 5,4 - Prescaler Select

The prescaler divides the 24 MHz input clock frequency to

provide the clock for the Baud Generator. (See Table 5-16).

TABLE 5-16. Prescaler Select

Bit 6 - Reserved

Read/Write 0.

Bit 7 - Baud Divisor Register Lock (LOCK)

When set to 1, accesses to the Baud Generator Divisor

back are disabled from non-extended mode.

In this case two scratchpad registers overlaid with LB-

GD(L) and LBGD(H) are enabled, and any attempted

CPU access of the Baud Generator Divisor Register

through LBGD(L) and LBGD(H) will access the Scratch-

Pad Registers instead. This bit must be set to 0 when

extended mode is selected.

5.13.5

Reserved Register

Upon reset, all bits in Bank 2 register with offset 05h are set to 0.

Bits 7-0 - Reserved

Read/Write 0.

5.13.6

TX_FIFO Current Level Register (TXFLV)

This read-only register returns the number of bytes in the

TX_FIFO. It can be used to facilitate programmed I/O

modes during recovery from transmitter underrun in one of

the fast infrared modes.

Bits 4-0 - Number of Bytes in TX_FIFO (TFL(4-0))

These bits specify the number of bytes in the TX_FIFO.

Bits 7,6 - Reserved

Read/Write 0.

Bit 5

Bit 4

Prescaler Value

1.625

Reserved

1.0

76543210

Reset

Required

and Status Register 2

(EXCR2)

Bank 2,

Extended Control and

PRESL0

PRESL1

Reserved

LOCK

Offset 04h

Reserved

76543210

Reset

Required

Bank 2,

TX_FIFO Current Level

TFL2

TFL4

TFL0

TFL1

TFL3

Extended Modes

Offset 06h

Reserved

PC87309VLJ データシート(PDF) 121 Page - National Semiconductor (TI)

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