HD404369F datasheet(49/117 Pages) RENESAS

49 / 117 page

HD404369 Series

Evaluation Chip Set and ZTAT

™/Mask ROM Product Differences

As shown in figure 27, the NMOS intermediate-voltage open drain pin circuit in the evaluation chip set

differs from that used in the ZTAT

™ microcomputer and built-in mask ROM microcomputer products.

Please note that although these outputs in the ZTAT

™ microcomputer and built-in mask ROM

microcomputer products can be set to high impedance by the combinations shown in table 23, these outputs

cannot be set to high impedance in the evaluation chip set.

Table 23

Program Control of High Impedance States

Set Value

DCR

PDR

Notes: * An asterisk indicates that the value may be either 0 or 1 and has no influence on circuit operation.

This applies to the ZTAT

™ and built-in mask ROM microcomputer NMOS open drain pins.

VCC

HLT

MIS3

DCR

PDR

CPU input

Input control signal

(a) Evaluation Chip Set Circuit Structure

Input control signal

(b) ZTAT

and Built-In Mask ROM Microcomputer Circuit Structure

HLT

DCR

PDR

CPU input

™

Figure 27 NMOS Intermediate-Voltage Open Drain Pin Circuits

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