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HD404369F データシート(PDF) 81 Page - Renesas Technology Corp

部品番号 HD404369F
部品情報  microcomputer has an A/D converter
PDF  117 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD404369F データシート(HTML) 81 Page - Renesas Technology Corp

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HD404369 Series
79
Transfer completion
(IFS
1)
Interrupts inhibited
IFS
0
SMR write
IFS = 1
Transmit clock
error processing
Normal
termination
←
←
Yes
No
Transmit clock error detection flowchart
Transmit clock error detection procedure
State
SCK pin (input)
Transmit clock
wait state
Transfer state
Transfer state
Transmit clock wait state
Noise
Transfer state has been
entered by the transmit clock
error. When SMR is written,
IFS is set.
Flag set because octal
counter reaches 000
Flag reset at
transfer completion
SMR write
IFS
12
3
4
56
78
Figure 61 Transmit Clock Error Detection
Registers for Serial Interface
The serial interface operation is selected, and serial data is read and written by the following registers.
 Serial Mode Register (SMR: $005)
 Serial Data Register (SRL: $006, SRU: $007)
 Port Mode Register A (PMRA: $004)
 Port Mode Register C (PMRC: $025)
 Miscellaneous Register (MIS: $00C)



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