PC87309VLJ datasheet(115/192 Pages) NSC

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Enhanced Serial Port with IR -UART2 (Logical Device 2)

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Bit 3 - Transmission Deferral (TX_DFR)

For a detailed description of the Transmission Deferral

see “Transmission Deferral” on page 107.

0: No transmission deferral enabled. (Default)

1: Transmission deferral enabled.

This bit is effective only if the Transmission FIFOs is en-

abled.

Bit 4 - Reserved

Read/Write 0.

Bits 7-5 - Mode Select (MDSL2-0)

These bits select the operational mode of the module

when in Extended mode, as shown in Table 5-10.

When the mode is changed, the transmission and re-

ception FIFOs are flushed, Link Status and Modem Sta-

tus Interrupts are cleared, and all of the bits in the

auxiliary status and control register are cleared.

TABLE 5-10. The Module Operation Modes

5.11.8

Link Status Register (LSR)

This register provides status information concerning the

data transfer. They are cleared when one of the following

events occurs:

The receiver is soft-reset.

The LSR register is read.

Upon reset this register assumes the value of 0x60h.

The bit definitions change depending upon the operation

mode of the module.

Bits 4 through 1 of the LSR are the error conditions that gen-

erate a Receiver Link Status interrupt whenever any of the

corresponding conditions are detected and that interrupt is

enabled.

The LSR is intended for read operations only. Writing to the

LSR is not permitted

Bit 0 - Receiver Data Available (RXDA)

Set to 1 when the Receiver Holding Register is full.

If the FIFOs are enabled, this bit is set when at least one

character is in the RX_FIFO.

Cleared when the CPU reads all the data in the Holding

Bit 1 - Overrun Error (OE)

This bit is set to 1 as soon as an overrun condition is de-

tected by the receiver.

Cleared upon read.

With FIFOs Disabled:

An overrun occurs when a new character is completely

received into the receiver front-end section and the CPU

has not yet read the previous character in the receiver

holding register. The new character is discarded, and

the receiver holding register is not affected.

With FIFOs Enabled:

An overrun occurs when a new character is completely

received into the receiver front-end section and the

RX_FIFO is full. The new character is discarded, and

the RX_FIFO is not affected.

Bit 2 - Parity Error (PE)

In UART, Sharp-IR and SIR modes, this bit is set to 1 if

the received data character does not have the correct

parity, even or odd as selected by the parity control bits

of the LCR register.

If the FIFOs are enabled, this error is associated with

the particular character in the FIFO that it applies to.

This error is revealed to the CPU when its associated

character is at the bottom of the RX_FIFO.

This bit is cleared upon read.

Bit 3 - Framing Error (FE)

In UART, Sharp-IR and SIR modes, this bit is set to 1

when the received data character does not have a valid

stop bit (i.e., the stop bit following the last data bit or par-

ity bit is a 0).

If the FIFOs are enabled, this Framing Error is associat-

ed with the particular character in the FIFO that it ap-

plies to. This error is revealed to the CPU when its

associated character is at the bottom of the RX_FIFO.

After a framing error is detected, the receiver will try to

resynchronize.

MDSL2

(Bit 7)

MDSL1

(Bit 6)

MDSL0

(Bit 5)

Operational Mode

UART mode (Default)

Reserved

Sharp-IR

011

SIR

Reserved

Consumer-IR

Reserved

76543210

Reset

Required

Link Status

Bank 0,

BRK

TXRDY

TXEMP

ER_INF

RXDA

Offset 05h

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