PC87309VLJ datasheet(117/192 Pages) NSC

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Enhanced Serial Port with IR -UART2 (Logical Device 2)

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5.11.10 Scratchpad Register (SPR)

This register shares a common address with the ASCR

In Non-Extended mode, this is a scratch register (as in the

16550) for temporary data storage.

5.11.11 Auxiliary Status and Control Register (ASCR)

This register shares a common address with the previous

one (SCR).

This register is accessed when the Extended mode of op-

eration is selected. The definition of the bits in this case is

dependent upon the mode selected in the MCR register,

bits 7 through 5. This register is cleared upon hardware re-

set Bits 2 and 6 are cleared when the transmitter is “soft re-

set”. Bits 0,1,4 and 5 are cleared when the receiver is “soft

reset”.

Bit 0 - RX_FIFO Time-Out (RXF_TOUT)

This bit is read only and set to 1 when an RX_FIFO tim-

eout occurs. It is cleared when a character is read from

the RX_FIFO.

Bit 1 -Reserved

Read/Write 0.

Bit 2 - Set End of Transmission (S_EOT)

In Consumer-IR mode this is the Set End of Transmis-

sion bit. When a 1 is written into this bit position before

writing the last character into the TX_FIFO, data trans-

mission is gracefully completed.

In this mode, if the CPU simply stops writing data into

the TX_FIFO at the end of the data stream, a transmitter

underrun is generated and the transmitter stops. In this

case this is not an error, but the software must clear the

underrun before the next transmission can occur. This

bit is automatically cleared by hardware when a charac-

ter is written to the TX_FIFO.

Bit 3 - Reserved

Read/Write 0.

Bit 4 - Reception Watchdog (RXWDG)

In Consumer-IR mode, this is the Reception Watchdog

(RXWDG) bit. It is set to 1 each time a pulse or pulse-

train (modulated pulse) is detected by the receiver. It

can be used by the software to detect a receiver idle

condition. It is cleared upon read.

Bit 5 - Receiver Active (RXACT)

In Consumer-IR Mode this is the Receiver Active (RX-

ACT) bit. It is set to 1 when an infrared pulse or pulse-

train is received. If a 1 is written into this bit position, the

bit is cleared and the receiver is deactivated. When this

bit is set, the receiver samples the infrared input contin-

uously at the programmed baud and transfers the data

to the RX_FIFO. See “Consumer-IR Reception” on

page 106.

Bit 6 - Infrared Transmitter Underrun (TXUR)

In the Consumer-IR mode, this is the Transmitter Un-

derrun flag. This bit is set to 1 when a transmitter under-

run occurs. It is always cleared when a mode other than

Consumer-IR is selected. This bit must be cleared, by

writing 1 into it, to re-enable transmission.

Bit 7 - Reserved

Read/Write 0.

5.12 BANK 1 – THE LEGACY BAUD GENERATOR

DIVISOR PORTS

This register bank contains two Baud Generator Divisor

Ports, and a bank select register.

The Legacy Baud Generator Divisor (LBGD) port provides

an alternate path to the Baud Divisor Generator register.

This bank is implemented to maintain compatibility with

16550 standard and to support existing legacy software

packages. In case of using legacy software, the addresses

0 and 1 are shared with the data ports RXD/TXD (see page

108). The selection between them is controlled by the value

of the BKSE bit (LCR bit 7 page 112).

TABLE 5-11. Bank 1 Register Set

76543210

Reset

Required

Scratchpad Register

(SCR)

Bank 0,

Scratch Data

Non-Extended Modes

Offset 07h

76543210

Reset

Required

Auxiliary Status

Bank 0,

Reserved

RXACT

TXUR

Reserved

S_EOT

RXWDG

RXF_TOUT

Extended Modes

Reserved

Offset 07h

Offset

Name

Description

00h

LBGD(L)

Legacy Baud Generator Divisor

Port (Low Byte)

01h

LBGD(H)

Legacy Baud Generator Divisor

Port (High Byte)

02h

Reserved

03h

LCR/

BSR

Link Control /

Bank Select Register

04h - 07h

Reserved

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