PC87309VLJ datasheet(116/192 Pages) NSC

116 / 192 page

Enhanced Serial Port with IR -UART2 (Logical Device 2)

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If the bit following the erroneous stop bit is 0, the receiv-

er assumes it to be a valid start bit and shifts in the new

character. If that bit is a 1, the receiver enters the idle

state and awaits the next start bit.

This bit is cleared upon read.

Bit 4 - Break Event Detected (BRK)

In UART, Sharp-IR and SIR modes this bit is set to 1

when a break event is detected (i.e. when a sequence

of logic 0 bits, equal or longer than a full character trans-

mission, is received). If the FIFOs are enabled, the

break condition is associated with the particular charac-

ter in the RX_FIFO to which it applies. In this case, the

BRK bit is set when the character reaches the bottom of

the RX_FIFO.

When a break event occurs, only one zero character is

transferred to the Receiver Holding Register or to the

RX_FIFO.

The next character transfer takes place after at least

one logic 1 bit is received followed by a valid start bit.

This bit is cleared upon read.

Bit 5 - Transmitter Ready (TXRDY)

This bit is set to 1 when the Transmitter Holding Regis-

ter or the TX_FIFO is empty.

It is cleared when a data character is written to the TXD

Bit 6 - Transmitter Empty (TXEMP)

This bit is set to 1 when the Transmitter Holding Regis-

ter or the TX_FIFO is empty, and the transmitter front-

end is idle.

Bit 7 - Error in RX_FIFO (ER_INF)

In UART, Sharp-IR and SIR modes, this bit is set to a 1

if there is at least 1 framing error, parity error or break

indication in the RX_FIFO.

This bit is always 0 in the 16450 mode.

This bit is cleared upon read.

5.11.9

Modem Status Register (MSR)

The function of this register depends on the selected oper-

ational mode. When a UART mode is selected, this register

provides the current-state as well as state-change informa-

tion of the status lines from the modem or data transmission

module.

When any of the infrared modes is selected, the register

function is controlled by the setting of the IRMSSL bit in the

IRCR2 (see page 124). If IRMSSL is 0, the MSR register

works as in UART mode. If IRMSSL is 1, the MSR register

returns the value 30 hex, regardless of the state of the mo-

dem input lines.

When loopback is enabled, the MSR register works similar-

ly except that its status input signals are internally driven by

appropriate bits in the MCR register since the modem input

lines are internally disconnected. Refer to at the MCR (see

page 114) and to the LOOP & ETDLBK bits at the EXCR1

(see page 120) for more information.

A description of the various bits of the MSR register, with

Loopback disabled and UART Mode selected, is provided

below.

When bits 0, 1, 2 or 3 is set to 1, a Modem Status Event

(MS_EV) is generated if the MS_IE bit is enabled in the IER

Bits 0 to 3 are set to 0 as a result of any of the following

events:

A hardware reset occurs.

The operational mode is changed and the IRMSSL bit

is 0.

The MSR register is read.

In the reset state, bits 4 through 7 are indeterminate as they

reflect their corresponding input signals.

Note: The modem status lines can be used as general

purpose inputs. They have no effect on the trans-

mitter or receiver operation.

Bit 0 - Delta Clear to Send (DCTS)

Set to 1, when the CTS input signal changes state.

This bit is cleared upon read.

Bit 1 - Delta Data Set Ready (DDSR)

Set to 1, when the DSR input signal changes state.

This bit is cleared upon read

Bit 2 - Trailing Edge Ring Indicate (TERI)

Set to 1, when the RI input signal changes state from

low to high.

This bit is cleared upon read

Bit 3 - Delta Data Carrier Detect (DDCD)

Set to 1, when the DCD input signal changes state.

1: DCD signal state changed.

Bit 4 - Clear To Send (CTS)

This bit returns the inverse of the CTS input signal.

Bit 5 - Data Set Ready (DSR)

This bit returns the inverse of the DSR input signal.

Bit 6 - Ring Indicate (RI)

This bit returns the inverse of the RI input signal.

Bit 7 - Data Carrier Detect (DCD)

This bit returns the inverse of the DCD input signal.

76543210

Reset

Required

Modem Status

Bank 0,

TERI

CTS

DSR

DCD

DCTS

DDSR

DDCD

Offset 06h

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