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L99DZ320 データシート(PDF) 52 Page - STMicroelectronics |
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L99DZ320 データシート(HTML) 52 Page - STMicroelectronics |
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52 / 146 page  Figure 17. Main operating modes Active Mode V1: ON Reset Generator: active Watchdog: active V1 Standby Mode V1: ON Reset Generator: active Watchdog: OFF (if Iv1<Icmp or ICMP = 1) Vbat Standby Mode V1: OFF Reset Generator: OFF(Nreset=low) Watchdog: OFF Wake-up Event Wake-up Event SPI command Vbat startup All registers Set to default, Chip Reset bit (RSTB) = 1 Vs > Vpor 7x Thermal Shutdown TSD2 OR 15 x WD fail SPI command OR 7x Thermal Shutdown 2 OR V1 short to GND (V1 < 2V for 4ms after switch ON) OR 15 x WD Failure 3.6 Configurable window watchdog During normal operation, the watchdog monitors the microcontroller within a programmable trigger cycle. After power-on or standby mode, the watchdog starts with a timeout (long open window tLW). The timeout allows the microcontroller to run its own setup and then to start the window watchdog by setting TRIG = 1. Subsequently, the microcontroller has to serve the watchdog by alternating the watchdog trigger bit within the safe trigger area Tswx. The trigger time is configurable by SPI. A correct watchdog trigger signal immediately starts the next cycle. After 8 watchdog failures in sequence, the V1 regulator is switched off for tv1off. After 7 additional watchdog failures the V1 regulator is turned off permanently and the device goes into forced VBAT_Standby mode. The status bit FORCED_SLEEP_WD (SR 8) is set. A wake-up is possible by any activated wake-up source. In case of a watchdog failure, the power outputs and V2 are switched off and the device enters fail-safe mode. All control registers are set to their failsafe values. The following diagrams illustrate the watchdog behavior of the device. The diagrams are split in 3 parts. The first diagram shows the functional behavior of the watchdog without any error. The second diagram covers the behavior covering all the error conditions, which can affect the watchdog behavior. The third diagram shows the transition in and out of debug mode. All 3 diagrams can be overlapped to get all the possible state transitions under all circumstances. For a better readability, they were split in normal operating, with errors and debug mode. L99DZ320 Functional description DS14235 - Rev 5 page 52/146 |
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