L99DZ320 datasheet(35/146 Pages) STMICROELECTRONICS

35 / 146 page

Symbol

Parameter

Test condition

Min. Typ. Max. Unit Item

TBit(RXD) ≤

5 Mb/s

Recessive bit

symmetry at RXDC

Conditions as TBit(RXD) ≤ 1 Mb/s,

Rectangular pulse signal TTXDC = 1200 ns, high

pulse 200 ns, low pulse 1000 ns

120

200

220

E.112

TBit(BUS) ≤

1 Mb/s

Recessive bit

symmetry at

CAN-Bus

5.5 V < VS < 18 V, RL = 60 Ω ±1%,

CL = 100 pF, CRXD = 15 pF,

VDIFF: 0.5 V (falling) - 0.9 V (rising),

TXD rise and fall time = 10 ns

(10% - 90%, 90% - 10%),

test signal to be applied on the TXD input of the

implementation is a square wave signal with a

positive duty cycle of 1/6 and a period of six times

the nominal recessive bit width.

Rectangular pulse signal TTXDC = 6000 ns, high

pulse 1000 ns, low pulse 5000 ns

935 1000 1030

E.113

TBit(BUS) ≤

2 Mb/s

Conditions as TBit(BUS) ≤ 1 Mb/s,

Rectangular pulse signal TTXDC = 3000 ns, high

pulse 500 ns, low pulse 2500 ns

435

500

530

E.114

TBit(BUS) ≤

5 Mb/s

Conditions as TBit(BUS) ≤ 1Mb/s,

Rectangular pulse signal TTXDC = 1200 ns, high

pulse 200 ns, low pulse 1000 ns

155

200

210

E.115

∆tREC ≤ 2 Mb/s

Receiver timing

symmetry (TBit(RXD) -

TBit(BUS))

5.5 V < VS < 18 V, RL = 60 Ω ±1%,

CL = 100 pF, CRXD = 15 pF,

Rectangular pulse signal TTXDC = 3000 ns, high

pulse 500 ns, low pulse 2500 ns

-65

E.116

∆tREC ≤ 5 Mb/s

5.5 V < VS < 18 V, RL = 60 Ω ±1%,

CL = 100 pF, CRXD = 15 pF,

Rectangular pulse signal TTXDC = 1200 ns, high

pulse 200 ns, low pulse 1000 ns

-45

E.117

tCAN(2)

CAN permanent

dominant time out

Tested by scan

700

µs

E.118

tWUP-VCansup

Time between

WUP(3) on the CAN

bus until VCansup

goes active

Wake-up pattern wake-up

70% VDIFF – 90% VCansup(min),

200

µs

E.049

tWUP-RXD

Time between

WUP(3) on the CAN

bus until RXD is

active (the CAN

signal is represented

at the RXD output)

Wake-up pattern wake-up

RXD output enabled

E.119

tVCANSUPlow

Filter time needed to

display CANSUPlow

flag

Tested by SCAN

µs

E.124

1. TBit(RXD) for the highest supported data rate has to be specified (1 Mb/s, 2 Mb/s, 5 Mb/s).

2. At the expiration of this filter time a flag is set.

3. Time starts with the end of last dominant phase of the WUP.

L99DZ320

Electrical specifications

DS14235 - Rev 5

page 35/146

L99DZ320 データシート(PDF) 35 Page - STMicroelectronics

L99DZ320 データシート(HTML) 35 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシートダウンロード

リンク URL

L99DZ320 データシート(PDF) 35 Page - STMicroelectronics

L99DZ320 データシート(HTML) 35 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシート ダウンロード

リンク URL

データシートダウンロード