L99DZ320 datasheet(82/146 Pages) STMICROELECTRONICS

82 / 146 page

Note:

Status registers that change status during communication could be cleared by the actual read and clear

operation and are not reported in actual communication or in the following communications. To avoid a loss of

any reported status, it is recommended just to clear the status registers that are already reported in the previous

communication (selective bitwise clear).

Advanced operation codes

To provide besides the separate write of all the control registers and the bitwise clear of all the status registers,

two advanced operation codes can be used to set all the control registers to the default value and to clear all the

status registers

A 'set all control registers to default' command is performed when an OpCode ‘11’ at address b’111111 is

performed.

Note:

Consider that potential device specific write-protected registers cannot be cleared with this command as

therefore a device power-on reset is needed.

A ‘clear all status registers’ command is performed when an OpCode ‘10’ at address b’111111 is performed.

Data in payload

The payload (data byte 1 to data byte 3) is the data transferred to the device with every SPI communication. The

payload always follows the OpCode and the address bits.

For write access the payload represents the new data written to the addressed register. For read and clear

operations the payload defines which bit of the addressed status register is cleared. In the case of a ‘1’ at the

corresponding bit position the bit is cleared.

For a read operation the payload is not used. For functional safety reasons it is recommended to set the unused

payload to ‘0’.

SDO frame

The data out frame consists of 32 bits (GSB + data bytes 1 to 3).

The first eight transmitted bits contain the device-related status information and are latched into the shift register

at the time of the communication starts. These 8 bits are transmitted at every SPI transaction.

The subsequent bytes contain the payload data and are latched into the shift register with the eight positive SCK

edges.

This could lead to an inconsistency of data between the GSB and the payload due to different shift register load

times. Anyway, no unwanted status register clear should appear, as status information should just be cleared with

a dedicated bit clear.

Figure 43. SDO frame

Global Status Byte (GSB)

DATA Byte 2

DATA Byte 1

RSTB

GSBN

SPIE

PLE

MSB

LSB

time

DATA Byte 3

time

Global status byte (GSB)

The bits (Bit 0 to Bit 4) represent a logical OR combination of bits located in the status registers. Therefore, no

direct read & clear can be performed on these bits inside the GSB.

L99DZ320

Serial peripheral interface (SPI)

DS14235 - Rev 5

page 82/146

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