L99DZ320 datasheet(57/146 Pages) STMICROELECTRONICS

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After turning on the V1 regulator (VSREG power on or wake-up from VBAT_Standby mode), NReset is kept low for

tRD in order to keep the microcontroller in reset until supply voltage is stable.

3.9

LIN bus interface

3.9.1

Features

•

LIN ISO 17987-4/2016 compliant transceiver

•

Meets hardware requirements for transceivers (version 1.3)

•

Data rate up to 20 kbit/s

•

GND disconnection fail-safe at module level

•

Off mode: does not disturb network

•

GND shift operation at system level

•

Microcontroller interface with CMOS compatible I/O pins

•

Internal pull-up resistor

•

ESD and transient immunity according to ISO7637 and EN / IEC61000-4-2

•

Matched output slopes and propagation delay

•

Wake-up behavior according to LIN2.2a and "Hardware requirements for LIN, CAN and flexray interfaces

(version 1.3)"

At VSREG > VPOR (that is VSREG Power-on Reset threshold), the LIN transceiver is enabled.

The LIN transmitter is disabled in case of the following errors:

•

Dominant TXDL time out

•

LIN permanent recessive

•

TSD1 on cluster 8 (global) if TSD_CLUSTER_EN = 1

•

TSD1 on any clusters if TSD_CLUSTER_EN = 0 (default)

The LIN receiver is not disabled in case of any failure condition (it is reactivated in case of FS by thermal

shutdown).

3.9.2

Error handling

The device LIN transceiver provides the following three error handling features:

1. Dominant TXDL time out

If TXDL is in dominant state (low) for t > tdom(TXDL) the transmitter is disabled, the status bit LIN_TXD_DOM

(SR7) is set.

The transmitter remains disabled until the status bit is cleared.

The TXD dominant timeout detection can be disabled via SPI (LIN_TXD_TOUT = 0).

2. Permanent recessive

If TXDL changes to dominant (low) state but the RXDL signal does not follow within t < tLIN the transmitter is

disabled, the status bit LIN_PERM_REC (SR7) is set.

The transmitter remains disabled until the status bit is cleared.

3. Permanent dominant

If the bus state is dominant (low) for t > tdom(bus) a bus permanent dominant failure is detected. The status bit

LIN_PERM_DOM (SR7) is set.

The transmitter is not disabled.

3.9.3

Wake-up from standby modes

In low-power modes (V1_Standby and VBAT_Standby) the L99DZ320 can receive two types of wake-up signals

from the LIN bus (configurable by SPI bit LIN_WU_CONFIG):

•

Recessive dominant recessive pattern with t > tdom_LIN (default, according to LIN 2.2a)

•

A dominant time of at least 150 μs must be identified as a wake-up. Shorter dominant times may wake-up

the device

•

State change recessive to dominant or dominant to recessive (according to LIN 2.1)

Note:

Dominant levels having duration less than a glitch filter time (it is defined 28 µs minimum, according to OEM

requirements version 1.3) have to be filtered and therefore they cannot wake-up the device.

L99DZ320

Functional description

DS14235 - Rev 5

page 57/146

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