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L99DZ320 データシート(PDF) 85 Page - STMicroelectronics |
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L99DZ320 データシート(HTML) 85 Page - STMicroelectronics |
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85 / 146 page ![]() The device information registers can be read by using OpCode ‘11’. After shifting out the GSB the 8-bit wide payload is transmitted. By reading device information registers a communication width which is minimum 16 bits plus a multiple by 8 can be used. After shifting out the GSB followed by the 8-bit wide payload a series of ‘0’ is shifted out at the SDO. Table 63. L99DZ320 information register map ROM address Description Access Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 3FH <Advanced op.> 3EH <GSB options> R 0 0 0 0 0 0 0 0 … 20H <SPI CPHA test> R 0 1 0 1 0 1 0 1 16H <WD bit pos. 4> R C0H 15H <WD bit pos. 3> R 7FH 14H <WD bit pos. 2> R C0H 13H <WD bit pos. 1> R 66H 12H <WD type 2> R 91H 11H <WD type 1> R 3CH 10H <SPI mode> R B0H … 0AH <Silicon ver.> R major revision minor revision … 05H <Device n.4> R 52H 04H <Device n.3> R 35H 03H <Device n.2> R 52H 02H <Device n.1> R 44H 01H <Device family> R 01H 00H <Company code> R 00H Device identification registers These registers represent a unique signature to identify the device and silicon version. <Company code>: 00H (STMicroelectronics) <Device family>: 01H (BCD power management) <Device n. 1>: 44H (ASCII code for D) <Device n. 2>: 52H (ASCII code for R) <Device n. 3>: 35H (ASCII code for 5) <Device n. 4>: 52H (ASCII code for R) SPI modes By reading out the <SPI mode> register general information of SPI usage of the device application registers can be read. Table 64. SPI mode registers Bit7 Bit6 Bit5 Bit 4 Bit 3 Bit 2 Bit1 Bit0 BR DL2 DL1 DL0 0 0 S1 S0 1 0 1 1 0 0 0 0 <SPI mode>: B0H (burst mode read available, 32-bit, no data consistency check) L99DZ320 Serial peripheral interface (SPI) DS14235 - Rev 5 page 85/146 |
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