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L99DZ320 データシート(PDF) 88 Page - STMicroelectronics |
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L99DZ320 データシート(HTML) 88 Page - STMicroelectronics |
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88 / 146 page  Table 69. WD bit position Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WB1 WB0 <WD bit pos. X> 0 0 Register is not used <WD bit pos. X> 0 1 WBA5 WBA4 WBA3 WBA2 WBA1 WBA0 <WD bit pos. 1> 0 1 0 0 0 0 0 1 <WD bit pos. 3> 0 1 1 1 1 1 1 1 Defines the register addresses of the WD trigger bits <WD bit pos. X> 1 0 WBA5 WBA4 WBA3 WBA2 WBA1 WBA0 Defines the stop address of the address range (previous<WD bit pos. X> is a WB = ‘01’). The consecutive <WD bitpos. X> has to be a WB = ‘11’ <WD bit pos. X> 1 1 0 WBP 4 WBP3 WBP2 WBP1 WBP0 <WD bit pos. 2> 1 1 0 0 0 0 0 0 <WD bit pos. 4> 1 1 0 0 0 0 0 0 Defines the binary bit position of the WD trigger bit within the register <WD bit pos 1>: 41H; watchdog trigger bit located at address 01H (CR18) <WD bit pos 2>: C0H; watchdog trigger bit location is bit0 <WD bit pos 3>: 7FH; watchdog trigger bit located at address 3FH (CR1) <WD bit pos 4>: C0H; watchdog trigger bit location is bit0 Device application registers (DAR) The device application registers are all accessible using OpCode ‘00’, ‘01’ and ‘10’. The functions of these registers are defined in the device specification. 4.2.4 Protocol failure detection To realize a protocol which covers certain failsafe requirements a basic set of failure detection mechanisms is implemented. Clock monitor During communication (CSN low to high phase) a clock monitor counts the valid SCK clock edges. If the SCK edges do not correlate with the SPI data length an SPIE is reported with the next command and the actual communication is rejected. By accessing the device information registers (OpCode = ‘11’) the clock monitor is set to a minimum of 16 SCK edges plus a multiple by 8 (for example 16, 25, 32, ...). Providing no SCK edge during a CSN low to high phase is not recognized as a SPIE. For a SPI burst read also the SPI data length plus multiple numbers of payloads SCK edges are assumed as a valid communication. SCK polarity (CPOL) check To detect the wrong polarity access via SCK the internal clock monitor is used. Providing first a negative edge on SCK during communication (CSN low to high phase) or a positive edge at last leads to an SPI error reported in the next communication and the actual data is rejected. SCK phase (CPHA) check L99DZ320 Serial peripheral interface (SPI) DS14235 - Rev 5 page 88/146 |
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