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L99DZ320 データシート(PDF) 86 Page - STMicroelectronics |
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L99DZ320 データシート(HTML) 86 Page - STMicroelectronics |
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86 / 146 page  SPI burst read Table 65. Burst read bit Bit 7 Description 0 BR not available 1 BR available The SPI burst read bit indicates if a burst read operation is implemented. The intention of a burst read is for example used to perform a device internal memory dump to the SPI master. The start of the burst read is like a normal read operation. The difference is that after the SPI data length the CSN is not pulled high and the SCK is continuously clocked. When the normal SCK max count is reached (SPI data length) the consecutive addressed data is latched into the shift register. This procedure is performed every time when the SCK payload length is reached. In case the automatic incremented address is not used by the device, undefined data is shifted out. An automatic address overflow is implemented when address 3FH is reached. The SPI burst read is limited by the CSN low timeout. SPI data length The SPI data length value indicates the length of the SCK count monitor which is running for all accesses to the device application registers. In case a communication frame with an SCK count is not equal to the reported one it will lead to a SPI error and the data will be rejected. Table 66. SPI data length Bit 6 Bit 5 Bit 4 Description DL2 DL1 DL0 0 0 0 Invalid 0 0 1 16-bit SPI 0 1 0 24-bit SPI 0 1 1 32-bit SPI 1 1 1 64-bit SPI Table 67. Data consistency check (parity-check) Bit 1 Bit 0 Description S1 S0 0 0 Not used 0 1 Parity used 1 0 CRC used 1 1 Invalid Watchdog definition (see also Section 2.4.7: Watchdog) In case a watchdog is implemented the default settings can be read out via the device information registers. Table 68. WD type/timing Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WD1 WD0 <WD type 1/2> 0 0 Register is not used L99DZ320 Serial peripheral interface (SPI) DS14235 - Rev 5 page 86/146 |
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