| データシートサーチシステム |
|
L99DZ320 データシート(PDF) 31 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
L99DZ320 データシート(HTML) 31 Page - STMicroelectronics |
|
31 / 146 page ![]() Table 25. CAN transmit data input: pin TXDC Symbol Parameter Test condition Min. Typ. Max. Unit Item VTXDCLOW Input voltage dominant level Active mode 1.0 1.45 2.0 V E.004 VTXDCHIGH Input voltage recessive level Active mode 1.2 1.85 2.3 V E.005 VTXDCHYS VTXDCHIGH - VTXDCLOW Active mode 0.2 0.7 V E.006 RTXDCPU TXDC pull-up resistor Active Mode 20 50 110 kΩ E.007 td,TXDC(dom-rec) TXDC - CANH,L delay time dominant - recessive RL = from 50 Ω to 65 Ω, 70 % VTXD – 30% VDIFF, 5.5 V ≤ VS ≤ 18 V, TXDC rise time = 10 ns (10% - 90%) 120 ns E.008 td,TXDC(rec-diff) TXDC - CANH,L delay time recessive - dominant RL = from 50 Ω to 65 Ω, 30 % VTXD – 70% VDIFF, 5.5 V ≤ VS ≤ 18 V, TXDC fall time = 10 ns (90% - 10%) 120 ns E.009 tdom(TXDC) TXDC dominant time-out Tested by scan 0.8 2 5 ms E.010 Table 26. CAN receive data output: pin RXDC Symbol Parameter Test condition Min. Typ. Max. Unit Item VRXDCLOW Output voltage dominant level Active mode, IRXDC = 2 mA 0 0.2 0.5 V E.011 VRXDCHIGH Output voltage recessive level Active mode, IRXDC = -2 mA V1-0.5 V1-0.2 V1 V E.012 tr,RXDC (1) RXDC rise time CL = 15 pF, 30% - 70% VRXDC 0 25 ns E.013 tf,RXDC(1) RXDC fall time CL = 15 pF, 70% - 30% VRXDC 0 25 ns E.014 td,RXDC(dom-rec)(1) CANH,L – RXDC delay time dominant - recessive CL = 15 pF, 30% VDIFF – 70% VRXDC 120 ns E.015 td,RXDC(rec - dom)(1) CANH,L – RXDC delay time recessive - dominant CL = 15 pF, 70% VDIFF – 30% VRXDC 120 ns E.016 1. Specified by design, not tested in production. Table 27. CAN transmitter dominant output characteristics Symbol Parameter Test condition Min. Typ. Max. Unit Item VCANHdom Single ended CANH voltage level in dominant state VTXDC = VTXDCLOW, RL = from 50 Ω to 65 Ω 2.75 3.5 4.5 V E.017 VCANLdom Single ended CANL voltage level in dominant state VTXDC = VTXDCLOW, RL = from 50 Ω to 65 Ω 0.5 1.5 2.25 V E.018 VDIFF,dom Differential output voltage in dominant state: VCANHdom- VCANLdom VTXDC = VTXDCLOW, RL = from 50 Ω to 65 Ω 1.5 2.0 3 V E.019 VDIFF_Arb Differential output voltage in dominant state during arbitration: VCANHdom-VCANLdom VTXDC = VTXDCLOW, RL = 2240 Ω 1.5 5 V E.099 L99DZ320 Electrical specifications DS14235 - Rev 5 page 31/146 |
|
リンク URL |
| ALLDATASHEETはお客様のビジネスに役立ちますか? [ DONATE ] |
Alldatasheetは | 広告 | お問い合わせ | プライバシーポリシー | データシートへのリンク | リンク交換 | メーカーリスト All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |