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L99DZ320 データシート(PDF) 92 Page - STMicroelectronics |
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L99DZ320 データシート(HTML) 92 Page - STMicroelectronics |
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92 / 146 page  Bit Name Description • CAN_TXD_DOM 0 = no error (default) 1 = error detected PLE is cleared by a read & clear command to all related bits in status registers 7. 27 FE Functional error bit The FE is a logical OR combination of errors coming from functional blocks. SR7 (0x7): • V2SC • DSMONx SR6 (0x6): • HSx_OC (x = 0, 7, .., 15) • HBx_LS_OC / HBx_HS_OC (x = 4, .., 6) • DSMON_HEAT SR5 (0x5)(3): • HSx_OL (x = 0, 7, .., 15) • HBx_LS_OL / HBx_HS_OL (x = 4, .., 6) • GH_OL 0 = no error (default) 1 = error detected FE is cleared by a read & clear command to all related bits in status registers 5, 6, 7 26 DE Device error bit DE is a logical OR combination of global errors related to the device. SR8 (0x8): • TSD1 SR7 (0x7): • VS_OV • VS_UV • VSREG_OV • VSREG_UV • CP_LOW 0 = no error (default) 1 = error detected DE is cleared by a read and clear command to all related bits in status registers 7 and 8 25 GW (2) Global warning bit GW is a logical OR combination of warning flags. Warning bits do not lead to any device state change or switch OFF of functions. SR7 (0x7): • V1FAIL • V2FAIL • CAN_RXD_REC • TW (3) • SPI_INV_CMD • SPI_SCK_CNT SR3 (0x3): • CAN_SUP_LOW 0 = no error (default) 1 = error detected GW is cleared by a read & clear command to all related bits in status registers 7 and 3. 24 FS Fail-safe L99DZ320 SPI Registers DS14235 - Rev 5 page 92/146 |
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