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L99DZ320 データシート(PDF) 41 Page - STMicroelectronics

部品番号 L99DZ320
部品情報  Automotive rear door device with CAN FD and LIN
PDF  146 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

L99DZ320 データシート(HTML) 41 Page - STMicroelectronics

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Table 44. CSN timing
Symbol
Parameter
Test condition
Min.
Typ.
Max.
Unit
Item
tCSN_HI,min
Minimum CSN HI time,
active mode
Transfer of SPI-command to Input register
0.5
μs
B.033
tCSNfail
CSN low timeout
Tested by scan
20
35
50
ms
B.034
Figure 10. SPI transfer timing diagram
1
2
3
4
5
6
7
0
0
1
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
1
0
1
CSN high to low: DO enabled
time
DI: data will be accepted on the rising edge of CLK signal
23
22
21
20
19
18
23
22
21
20
19
18
23
22
21
20
19
18
X
X
X
X
X
X
CSN
CLK
DI
DO
Input
Data
Register
DO: data will change on the falling edge of CLK signal
fault bit
new data
old data
CSN low to high: actual data is
transferred to output power switches
25
time
time
time
time
31
30
29
28 27 26 25
24
X
X
5
4
3
2
0
30
31
1
31
30
29
28 27 26 25
24
X
X
5
4
3
2
0
30
31
1
31
30
29
28 27 26 25
24
X
X
5
4
3
2
0
30
31
1
CSN high to low: DO enabled
DI: data will be accepted on the rising edge of CLK signal
time
The SPI can be driven by a microcontroller with its SPI peripheral running in the following mode: CPOL = 0 and
CPHA = 0.
For this mode input data is sampled by the low to high transition of the clock CLK, and output data is changed
from the high to low transition of CLK.
Figure 11. SPI input timing
0.8 VCC
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
0.2 VCC
Valid
Valid
CSN
CLK
DI
t
set CSN
t
CLKH
t
set CLK
t
CLKL
t
hold DI
t
set DI
L99DZ320
Electrical specifications
DS14235 - Rev 5
page 41/146



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