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SPC58EE80C3 データシート(PDF) 65 Page - STMicroelectronics |
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SPC58EE80C3 データシート(HTML) 65 Page - STMicroelectronics |
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65 / 154 page  DS11646 Rev 4 65/154 SPC58EEx, SPC58NEx Electrical characteristics 66 tSETTLING CC D Settling time after mux change Analog inputs are muxed HPF = ON —— 2* δGROUP + 3*fADCD_S — HPF = OFF — — 2* δGROUP + 2*fADCD_S — tODRECOVERY CC D Overdrive recovery time After input comes within range from saturation HPF = ON —— 2* δGROUP + fADCD_S — HPF = OFF — — 2* δGROUP — CS_D CC D S/D ADC sampling capacitance after sampling switch(16) GAIN = 1, 2, 4, 8 — — 75*GAIN fF GAIN = 16 — — 600 fF IBIAS CC D Bias consumption At least 1 ADCD enabled —— 5 mA IADV_D CC C VDD_HV_ADV power supply current (each ADC) ADCD enabled — — 3.5 mA ΣIADR_D CC C Sum of all ADC reference consumption(17) ADCD enabled — — 80 µA 1. For input voltage above the maximum and below the clamp voltage of the input pad, there is no latch-up concern, and the signal will only be ‘clipped’. 2. VINP is the input voltage applied to the positive terminal of the SDADC. 3. VINM is the input voltage applied to the negative terminal of the SDADC. 4. Maximum input of 166.67 KHz supported with reduced accuracy. See SNR specifications. 5. When using a GAIN setting of 16, the conversion result will always have a value of zero in the least significant bit. This gives an effective resolution of 15 bits. 6. The absolute value of the ADC gain error (| δGAIN|) after calibration is applicable in differential mode only. In single-ended mode after calibration, this value should be considered as 25mV. 7. Offset and gain error due to temperature drift can occur in either direction (+/-) for each of the SDADCs on the device. 8. Calibration of gain is possible when gain = 1. Offset Calibration should be done with respect to 0.5*VDD_HV_ADR_D for "differential mode" and "single ended mode with negative input=0.5*VDD_HV_ADR_D". Offset Calibration should be done with respect to 0 for "single ended mode with negative input=0". Both offset and Gain Calibration is guaranteed for ±5% variation of VDD_HV_ADR_D, ±10% variation of VDD_HV_ADV, and ± 50 °C temperature variation. 9. Conversion offset error must be divided by the applied gain factor (1, 2, 4, 8, or 16) to obtain the actual input referred offset error. 10. This parameter is guaranteed by bench validation with a small sample of devices across process variations, and tested in production to a value of 3 dB less. 11. S/D ADC is functional in the range 3.6 V < VDD_HV_ADV < 4.0 V and, SNR parameter degrades by 12 dB. Degraded SNR value based on simulation and granted by design. 12. All channels of all SD-ADCs are impacted with same degradation, independently from the ADC and the channel subject to current injection. 13. SNR value guaranteed only if external noise on the ADC input pin is attenuated by the required SNR value in the frequency range of fADCD_M - fADCD_S to fADCD_M + fADCD_S, where fADCD_M is the input sampling frequency, and fADCD_S is the output sample frequency. A proper external input filter should be used to remove any interfering signals in this frequency range. 14. The ±1% passband ripple specification is equivalent to 20 * log10 (0.99) = 0.087 dB. Table 29. SDn ADC electrical specification (continued) Symbol C Parameter Conditions Value Unit Min Typ Max |
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