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SPC58EE80C3 データシート(PDF) 95 Page - STMicroelectronics

部品番号 SPC58EE80C3
部品情報  32-bit Power Architecture microcontroller for automotive ASIL-D applications
PDF  154 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
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SPC58EE80C3 データシート(HTML) 95 Page - STMicroelectronics

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DS11646 Rev 4
95/154
SPC58EEx, SPC58NEx
Electrical characteristics
128
3.18.1.2
Nexus interface timing
Table 50. Nexus debug port timing
#
Symbol
C
Characteristic
Value(1)
Unit
Min
Max
7tEVTIPW CC D EVTI pulse width
4
tCYC(2)
8tEVTOPW CC D EVTO pulse width
40
ns
9tTCYC
CC D
TCK cycle time
2(3),(4)
—tCYC(2)
Absolute minimum TCK cycle time(5) (TDO sampled on posedge
of TCK)
60(6)
ns
Absolute minimum TCK cycle time(7) (TDO sampled on negedge
of TCK)
30(6)
11
tNTDIS
CC D TDI data setup time
5
ns
12
tNTDIH
CC D TDI data hold time
5
ns
13
tNTMSS CC D TMS data setup time
5
ns
14
tNTMSH CC D TMS data hold time
5
ns
15
CC D TDO propagation delay from falling edge of TCK(8)
—25
ns
16
CC D
TDO hold time with respect to TCK falling edge (minimum TDO
propagation delay)
2.25
ns
1. Nexus timing specified at VDD_HV_IO_JTAG = 3.0 V to 5.5 V, and maximum loading per pad type as specified in the I/O
section of the data sheet.
2. tCYC is system clock period.
3. Achieving the absolute minimum TCK cycle time may require a maximum clock speed (system frequency / 8) that is less
than the maximum functional capability of the design (system frequency / 4) depending on the actual peripheral frequency
being used. To ensure proper operation TCK frequency should be set to the peripheral frequency divided by a number
greater than or equal to that specified here.
4. This is a functionally allowable feature. However, it may be limited by the maximum frequency specified by the Absolute
minimum TCK period specification.
5. This value is TDO propagation time 36 ns + 4 ns setup time to sampling edge.
6. This may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the
design (system frequency / 4) depending on the actual system frequency being used.
7. This value is TDO propagation time 16 ns + 4 ns setup time to sampling edge.
8. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.



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