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SPC58EE80C3 データシート(PDF) 97 Page - STMicroelectronics |
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SPC58EE80C3 データシート(HTML) 97 Page - STMicroelectronics |
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97 / 154 page  DS11646 Rev 4 97/154 SPC58EEx, SPC58NEx Electrical characteristics 128 3.18.1.3 Aurora LVDS interface timing 3.18.1.4 Aurora debug port timing Table 51. Aurora LVDS interface timing specifications Symbol C Parameter Value Unit Min Typ Max Data Rate — SR T Data rate — — 1250 Mbps STARTUP tSTRT_BIAS CC T Bias startup time(1) —— 5 µs tSTRT_TX CC T Transmitter startup time(2) —— 5 µs tSTRT_RX CC T Receiver startup time(3) —— 4 µs 1. Startup time is defined as the time taken by LVDS current reference block for settling bias current after its pwr_down (power down) has been deasserted. LVDS functionality is guaranteed only after the startup time. 2. Startup time is defined as the time taken by LVDS transmitter for settling after its pwr_down (power down) has been deasserted. Here it is assumed that current reference is already stable (see Bias start-up time). LVDS functionality is guaranteed only after the startup time. 3. Startup time is defined as the time taken by LVDS receiver for settling after its pwr_down (power down) has been deasserted. Here it is assumed that current reference is already stable (see Bias start-up time). LVDS functionality is guaranteed only after the startup time. Table 52. Aurora debug port timing # Symbol C Characteristic Value Unit Min Max 1tREFCLK CC T Reference clock frequency 625 1250 MHz 1a tMCYC CC T Reference clock rise/fall time — 400 ps 2tRCDC CC D Reference clock duty cycle 45 55 % 3JRC CC D Reference clock jitter — 40 ps 4tSTABILITY CC D Reference clock stability 50 — PPM 5 BER CC D Bit error rate — 10–12 — 6JD SR D Transmit lane deterministic jitter — 0.17 OUI 7JT SR D Transmit lane total jitter — 0.35 OUI 8SO CC T Differential output skew — 20 ps 9SMO CC T Lane to lane output skew — 1000 ps 10 OUI CC D Aurora lane unit interval(1) 625 Mbps 1600 1600 ps D 1.25 Gbps 800 800 1. ± +/-100 PPM |
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