SPC58EE80C3 datasheet(20/154 Pages) STMICROELECTRONICS

20 / 154 page

Electrical characteristics

SPC58EEx, SPC58NEx

20/154

DS11646 Rev 4

3.3.1

Power domains and power up/down sequencing

The following table shows the constraints and relationships for the different power domains.

Supply1 (on rows) can exceed Supply2 (on columns), only if the cell at the given row and

column is reporting ‘ok’. This limitation is valid during power-up and power-down phases, as

well as during normal device operation.

5. In the range [1.14-1.08]V, the device functionality and specifications are granted and the device is expected to receive a

flag by the internal LVD100 monitors to warn that the regulator (internal or external), providing the VDD_LV supply, exited the

expected operating conditions. If the internal LVD100 monitors are disabled by the application, then an external voltage

monitor with minimum threshold of VDD_LV(min) = 1.08 V measured at the device pad, has to be implemented. Refer to

Section 3.16.3: Voltage monitors for the list of available internal monitors and to the Reference Manual for the

configurability of the monitors.

6. Core voltage can exceed 1.26 V with the limitations provided in Section 3.2: Absolute maximum ratings, provided that

HVD134_C monitor reset is disabled.

7. 1.260 V - 1.290 V range allowed periodically for supply with sinusoidal shape and average supply value below or equal to

1.236 V at the given temperature profile.

8. S/D ADC is functional in the range 3.0 V < VDD_HV_ADV < 4.0 V and 3.0 V < VDD_HV_ADR_D < 4.0 V, but precision of

conversion is not guaranteed.

9. Full device lifetime. I/O and analog input specifications are only valid if the injection current on adjacent pins is within these

limits. See Section 3.2: Absolute maximum ratings for maximum input current for reliability requirements.

10. The I/O pins on the device are clamped to the I/O supply rails for ESD protection. When the voltage of the input pins is

above the supply rail, current will be injected through the clamp diode to the supply rails. For external RC network

calculation, assume typical 0.3 V drop across the active diode. The diode voltage drop varies with temperature.

11. The limits for the sum of all normal and injected currents on all pads within the same supply segment can be found in

Section 3.8.3: I/O pad current specifications.

12. Positive and negative Dynamic current injection pulses are allowed up to this limit, with different specifications for I/O, ADC

accuracy and analog input. See the dedicated chapters for the different specification limits. See the Absolute Maximum

Ratings table for maximum input current for reliability requirements. Refer to the following pulses definitions: Pulse1 (ISO

7637-2:2011), Pulse 2a(ISO 7637-2:2011 5.6.2), Pulse 3a (ISO 7637-2:2011 5.6.3), Pulse 3b (ISO 7637-2:2011 5.6.3).

Table 6. PRAM wait states configuration

PRAMC WS

Clock Frequency (MHz)

1< 180

0< 120

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