33394 datasheet(19/44 Pages) FREESCALE

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33394

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

the trip–off temperature. The output will periodically turn on

and off until either the die temperature decreases or until the

fault condition is removed. If the VSEN output goes into

over—temperature shutdown, it does not impact the operation

of any of the other outputs (assuming that no other package

thermal or VPRE current limit specifications are violated).

Fault information is reported through the SPI communication

interface (see Figure 8).

4.10. Resets To Microprocessor

/PORESET – Power On Reset, /PRERESET — Pre Reset,

/HRESET– Hardware Reset. All the Reset pins are open drain

‘active low’ outputs, capable of sinking 1.0 mA current and

able to withstand +7.0 V. See Figure 1 and Figure 20 for

recommended pull–up resistor values and their connection.

The /PORESET pin is pulled up to the VKAM voltage by a

pull up resistor. It is connected to the microprocessor Power

On Reset (POR) pin, and is normally high. During initial battery

connect the /PORESET is held to ground by the 33394. After

the VKAM supply is in regulation and an internal 10 ms timer

has expired, the /PORESET is released. If VKAM goes out of

regulation the device will first pull the /PORESET and

/PRERESET followed by a 0.7

µs delay then /HRESET. By

/HRESET low VDDH, VDD3_3 and VDDL will start a power

down sequence. When the fault is removed a standard power

up sequence is initiated. The VKAM linear regulator output

must be out of regulation for greater than 20

µs before

/PORERSET and /PRERESET (with /HRESET 0.7

µs

delayed) are pulled low. If a fault occurs on VKAM in the

Key–Off Mode (when the VIGN is off) and the fault is then

removed the VKAM will regulate but /PORESET will not be

released until Key–On (asserting VIGN pin) allows the 10 ms

timer to run.

The Reset signals (/PRERESET, /HRESET) are not

asserted when the 33394 enters Sleep Mode by asserting the

/SLEEP pin. When exiting out of Sleep Mode the 33394

asserts the Resets (/PRERESET, /HRESET) during the power

up sequence.

The /PRERESET and /HRESET pins are pulled up to the

VKAM (see Figure 1) or to VDDL (see Figure 20). Refer to

section

Application

Information,

paragraph

5.3.

Selecting Pull–Up Resistors for detailed description of

these two connection scenarios. The 33394 monitors the main

supply voltages VDDH, VDD3_3 and VDDL. If any of these

voltages falls out of regulation limits the /PRERESET will be

pulled down followed by the /HRESET after 0.7

µs delay, and

the power down sequence will be initiated. There are several

different scenarios how to connect the /PRERESET and

/HRESET

pins

the

microprocessor.

Typically

the

/PRERESET pin will be connected to the IRQ0 pin of the

microprocessor, and the /HRESET to the microprocessor

/HRESET pin (see Figure 5). The VDDH, VDD3_3 and VDDL

linear regulator outputs must be out of regulation for greater

than 20

µs before /PRERESET (with /HRESET 0.7 µs

delayed) are pulled low.

4.11. Hardware Reset Timer (HRT)

The HRT pin is used to set the delay between VDDH,

VDD3_3 and VDDL active and stable and the release of the

/HRESET and /PRERESET outputs. An external resistor and

capacitor is used to program the timer. To minimize quiescent

current during power down modes, the RC timer current

should be drawn from one of the VDD supplies (see Figure 1).

The threshold on the HRT pin has zero temperature coefficient

and is set at 2.5 V.

4.12. Power Up/Down Sequencing

The 33394 power up sequence is specifically designed to

meet the power up and power down requirements of the

MPC565 microprocessor. The MPC565 processor requires

that VDDH remain within 3.1 volts of VDDL during power up

and can not lag VDDL by more than 0.5 volts. This condition

is met by the 33394 regardless of load impedance. It is critical

to note that the 33394 under normal conditions is designed to

supply VKAM prior to the power up sequence on VDDH,

VDD3_3 and VDDL. During power up and power down

sequencing /PRERESET and /HRESET are held low. Power

up and power down sequencing is implemented in six steps.

During this process the reference voltage for VDDH, VDD3_3

and VDDL is ramped up in six steps. Minimum power up/down

time is dependent on the internal clock and is 800

µs.

Maximum power up/down time is also dependent on load

impedance. During the power up/down cycle, voltage level

requirements for each step of VDDH, VDD3_3 and VDDL

must be met before the supply may advance to the next

voltage level. Hence VDDH and VDDL will remain within the

3.1/0.5 V window. Figure 6 illustrates a typical power up and

down sequence.

4.13. Regulator Enable Function (REGON)

This feature allows the microcontroller to select the delayed

shut down of the 33394 device. It holds off the activation of the

Reset signals, to the microcontroller, after the VIGN signal has

transitioned and signals the request to shutdown the VDDH,

VDD3_3, VDDL, VSEN and the VREFn supplies. This allows

the microcontroller to delay a variable amount of time, after

sensing that the VIGN signal has transitioned and signaled the

request to shutdown the regulated supplies. This time can be

used to store data to EPROM memory, schedule an orderly

shutdown of peripherals, etc. The microcontroller can then

drive the REGON signal, to the 33394, to the low logic state,

to turn off the regulators (except for the VKAM supply).

4.14. Regulator Shutdown Function (/SLEEP)

This feature allows for an external control element (e.g.

microprocessor) to shut down the 33394 regulators, even if

the VIGN signal (or REGON) is active, by asserting the

/SLEEP pin from high to low (falling edge transition). In this

case the 33394 initiates the power down sequence, but the

Reset signals (/PRERESET, /HRESET) are not asserted. This

allows the microprocessor to continue to execute code when

it is supplied only from the Keep Alive supply VKAM. When the

microprocessor exits sleep state by pulling /SLEEP pin high

the Resets (/PRERESET, /HRESET) are asserted during the

power up sequence.

The /SLEEP pin has an internal pull down, therefore when

its functionality is not used this pin can be either pulled up to

VKAM, VBAT, pulled down to ground or left open.

The /SLEEP pin should not be pulled up to VDDH.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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