SPC58EE80C3 datasheet(116/154 Pages) STMICROELECTRONICS

116 / 154 page

Electrical characteristics

SPC58EEx, SPC58NEx

116/154

DS11646 Rev 4

Figure 38. MII receive signal timing diagram

3.18.3.2

MII transmit signal timing (TXD[3:0], TX_EN, TX_ER, TX_CLK)

The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz +1%.

There is no minimum frequency requirement. The system clock frequency must be at least

equal to or greater than the TX_CLK frequency.

The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from

either the rising or falling edge of TX_CLK, and the timing is the same in either case. This

option allows the use of non-compliant MII PHYs.

Refer to the SPC58xEx 32-bit Power Architecture microcontroller reference manual’s

Ethernet chapter for details of this option and how to enable it.

Note:

In the following table, all timing specifications are referenced from TX_CLK = 1.4 V to the

valid output levels, 0.8 V and 2.0 V.

RX_CLK (input)

RXD[3:0] (inputs)

RX_DV

RX_ER

Table 62. MII transmit signal timing

Symbol

Characteristic

Value(1)

Unit

Min

Max

CC D TX_CLK to TXD[3:0], TX_EN, TX_ER invalid

—

CC D TX_CLK to TXD[3:0], TX_EN, TX_ER valid

—

CC D TX_CLK pulse width high

35%

65%

TX_CLK period

CC D TX_CLK pulse width low

35%

65%

TX_CLK period

1. Output parameters are valid for CL = 25 pF, where CL is the external load to the device. The internal package capacitance

is accounted for, and does not need to be subtracted from the 25 pF value

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