ADA4255ACPZ-R7 datasheet(29/64 Pages) AD

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Data Sheet

ADA4255

THEORY OF OPERATION

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Rev. 0 | 29 of 64

OUTPUT RIPPLE CALIBRATION

CONFIGURATION

The amplifiers inside the ADA4255 achieve zero drift by using a

technique commonly referred to as chopping. When chopping is

used to null the offset of an amplifier, the unchopped offsets are

modulated to the frequency at which the chopping is performed. All

chopping amplifiers feature this phenomenon, which is commonly

referred to as ripple.

The ADA4255 instrumentation amplifier features a proprietary cali-

bration routine that reduces the residual voltage ripple at the output

of the ADA4255 by nulling the internal offsets of all amplifiers.

This calibration occurs automatically when the ADA4255 is initially

powered on, after a POR_HV event, or after a soft reset occurs.

Further calibrations can be performed either on a scheduled or

triggered basis.

While the ADA4255 is calibrating, the SW_A1, SW_A2, SW_B1,

and SW_B2 bits (Register INPUT_MUX) are temporarily opened

and the amplifier inputs are internally connected to AVSS through

the SW_C1 and SW_C2 bits (Register INPUT_MUX). After a cali-

bration completes, the switches return to their previous states.

Two calibration types can be selected via the CAL_SEL bit

(Register TEST_MUX): full calibration or quick calibration.

A full calibration sequentially calibrates each individual amplifier

and fully computes a new calibration code. This calibration takes

approximately 85 ms. Full calibration always occurs after power-up,

after a POR_HV event, or after a soft reset.

A quick calibration calculates a new calibration code for all amplifi-

ers at the same time. The calibration code of each amplifier is then

adjusted by an incremental amount. This type of calibration takes

approximately 8 ms.

By default, calibrations only occur after power-up, after a POR_HV

event, or after a reset. Additional scheduled calibrations are config-

ured via CAL_EN (Register TEST_MUX), or are triggered via the

TRIG_CAL bit (Register TRIG_CAL).

When scheduled calibrations are configured via the CAL_EN bits

(Register TEST_MUX), the selected calibration type occurs at the

rate configured via the CAL_EN bits.

Calibrations can also be manually triggered via the TRIG_CAL bit

(Register TRIG_CAL).

The internal offsets, which are nulled by the ADA4255 calibration

routine, can change when the circuit or the environmental condi-

tions change. Changes in temperature, supply voltage, common-

mode input voltage, time, and so on, can all cause an increase in

output ripple. Recalibrations, either triggered or scheduled, renull

internal offsets and reduce residual output ripple.

During a calibration, noise can limit the ability of the ADA4255

to fully null internal offsets and fully reduce the residual output

ripple. Proper decoupling and shielding techniques help ensure ac-

curate calibrations. Avoid large input transients during calibrations.

Calibrations typically reduce the output ripple to <200 μV rms, but

results as high as 5 mV rms can be observed in the presence of

noise or input transients. If excessive residual ripple is detected,

subsequent calibrations can be performed to reduce the output

ripple.

ADC synchronization and simple filtering, either passive or active,

are also effective methods in reducing residual output ripple. These

techniques are discussed in detail in the External Clock Synchroni-

zation section and the Output Amplifier section.

GENERAL-PURPOSE INPUTS AND OUTPUTS

(GPIOS)

The ADA4255 features several multifunction GPIOx pins. These

GPIOx pins can be configured to either read a logic input or output

a logic signal. A GPIOx pin is configured as an input or an output

using the GPIO_DIR register. The bit position in the GPIO_DIR

at Position 0 controls the GPIO0 direction.

The GPIO_DATA register sets the GPIO output when a GPIOx pin

is configured as an output. The GPIO_DATA register also reads

the data at the GPIOx pin when a GPIO is configured as an input.

The bit field position in the GPIO_DATA register corresponds to the

GPIOx pin number. For example, the bit at Position 0 corresponds

to GPIO0.

The ADA4255 GPIOx pins can be configured to perform additional

special functions.

Each GPIO can be configured as an output to extend the chip

select signal from the SPI master to other slave devices. This

special functionality is referred to as sequential chip select and is

particularly useful in limiting the number of communication lines

that need to be routed and/or isolated in a system. This special

functionality is controlled by the SCS register.

GPIO0 and GPIO1 can also be configured as external multiplexer

control signals. This function is enabled in the special function

outputs, the EXT_MUX bit field in the GAIN_MUX register controls

the state of GPIO0 and GPIO1, allowing the gain and the external

mux setting to be modified with one write operation.

GPIO2 can be configured to output a calibration busy signal. This

function is enabled via the CAL_BUSY_OUT bit

(Register SF_CFG). The calibration busy signal indicates that the

ADA4255 is performing a calibration routine. GPIO2 must be con-

figured as an output to use this special function.

GPIO3 can be configured to output a fault interrupt signal. This

signal is an OR function of all the analog and digital error indicators

found in the ANALOG_ERR and DIGITAL_ERR registers. This

function is enabled via the FAULT_INT_OUT bit

(Register SF_CFG). GPIO3 must be configured as an output to use

this special function.

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