ADA4255ACPZ-R7 datasheet(46/64 Pages) AD

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Data Sheet

ADA4255

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GAIN MULTIPLEXER REGISTER (GAIN_MUX)

DETAILS

Table 10. GAIN_MUX Register Details (Register 0x00)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bit Name

G[3:0]

Reserved

EXT_MUX[1:0]

Access

R/W

Reserved

R/W

Reset

Reserved

Bit 7, G4—Output Amplifier Scaling Gain

(1.375 V/V)

Setting the G4 bit to 1 configures the output amplifier in a scaling

gain of 1.375 V/V. This configuration scales the input amplifier gain,

G[3:0] (Bits[6:3]), by 1.375 V/V. The G4 bit takes precedence over

the G5 bit, located in the TEST_MUX register. Setting the G4 bit

to 0 configures the output amplifier in either a gain of 1 V/V or

1.25 V/V, depending on the value written to the G5 bit. These gain

settings are summarized in Table 11.

Table 11. Output Amplifier Scaling Gain Settings

G5 Bit

G4 Bit

Output Amplifier Scaling Gain (V/V)

1.375

1.25

1 X means don't care.

Bits[6:3], G[3:0]—Input Amplifier Gain Setting

The G[3:0] bits set the gain of the input amplifier, as shown in

Table 12. The overall gain is scaled by the output amplifier scaling

gain, which is configured using the G4 bit and the G5 bit. The

default input amplifier gain is 1/16 V/V.

Table 12. Register Values for Input Amplifier Gains

Input Amplifier Gain (V/V)

Bits in the G[3:0] Bit Field

1/16

1/8

1/4

1/2

128

Reserved

Bits[1:0], EXT_MUX[1:0]—External Multiplexer

Control

When external multiplexer control is enabled using the EXT_

MUX_EN bits in Register 0x0C, and GPIO1 and/or GPIO0 are

configured as outputs using the GPIO_DIR bits in Register 0x08,

EXT_MUX[1:0] sets the output of GPIO1 and/or GPIO0. This setup

simplifies communication in externally multiplexed applications be-

cause both the gain and the external multiplexer can be configured

with a single SPI write to the GAIN_MUX register. Multiplexers

larger than 4 to 1 are supported by using additional GPIOx pins and

additional SPI writes.

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