ADA4255ACPZ-R7 datasheet(63/64 Pages) AD

63 / 64 page

Data Sheet

ADA4255

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Rev. 0 | 63 of 64

TRIGGER CALIBRATION REGISTER

(TRIG_CAL) DETAILS

Table 37. TRIG_CAL Registers Details (Register 0x2A)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Bit Name

Reserved

TRIG_CAL

Access

Reserved

Reset

Reserved

Bit 0, TRIG_CAL—Trigger Calibration Input

Setting TRIG_CAL to 1 initiates a calibration sequence when

scheduled calibrations are disabled via CAL_EN. The type of cali-

bration that is triggered can be configured via the CAL_SEL bits

(Register TEST_MUX). The TRIG_CAL bit is self clearing.

MASTER CLOCK COUNT REGISTER

(M_CLK_CNT) DETAILS

Table 38. M_CLK_CNT Registers Details (Register 0x2E)

Bit 7

Bit 6

Bit 5

Bit 4 Bit 3 Bit 2

Bit 1

Bit 0

Bit Name

M_CLK_CNT[7:0]

Access

Bits[7:0], M_CLK_CNT[7:0]—Master Clock

Count

M_CLK_CNT contains a master clock counter that increments

when M_CLK_CNT_ERR is cleared to 0. The counter is updated

every 512 µs. Setting M_CLK_CNT_ERR to 1 stops this register

from updating.

DIE REVISION IDENTIFICATION REGISTER

(DIE_REV_ID) DETAILS

Table 39. DIE_REV_ID Registers Details (Register 0x2F)

Bit 7

Bit 6

Bit 5

Bit 4 Bit 3 Bit 2

Bit 1

Bit 0

Bit Name

DIE_REV_ID[7:0]

Access

Reset

Bits[7:0], DIE_REV_ID[7:0]—Die Revision

Identification Number

DIE_REV_ID contains a fixed value of 0x30 that can be used to

verify the SPI communication with the ADA4255.

DEVICE IDENTIFICATION REGISTERS

(PART_ID) DETAILS

Table 40. PART_ID Registers Details (Register 0x64 through Register 0x68)1

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x64

PART_ID[39:32]

0x65

PART_ID[31:24]

0x66

PART_ID[23:16]

0x67

PART_ID[15:8]

0x68

PART_ID[7:0]

Access

PART_ID[39:0]—Part ID Number

The PART_ID register contains a unique device identification num-

ber that is programmed at the factory.

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