ADA4255ACPZ-R7 datasheet(48/64 Pages) AD

48 / 64 page

Data Sheet

ADA4255

analog.com

Rev. 0 | 48 of 64

CLOCK SYNCHRONIZATION CONFIGURATION

Table 14. SYNC_CFG Register Details (Register 0x02)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bit Name

CLK_CP_SEL

CLK_OUT_SEL

Reserved

SYNC_POL

Reserved

SYNC[2:0]

Access

R/W

Reserved

R/W

Reset

Reserved

Bit 7, CLK_CP_SEL—Charge Pump Clock

Select

The charge pump of the ADA4255 runs at 16 MHz by default.

Alternatively, setting CLK_CP_SEL to 1 changes the charge pump

frequency to 8 MHz.

Bit 6, CLK_OUT_SEL—Clock Output Select

The ADA4255 1 MHz master clock is divided down to

125 kHz internally and is used by the zero drift amplifiers. When

the INT_CLK_OUT bit in Register 0x0C is set to 1, setting

CLK_OUT_SEL to 1 outputs the divided down 125 kHz clock on

GPIO4. Clearing CLK_OUT_SEL to 0 outputs the 1 MHz master

clock on GPIO4.

Bit 4, SYNC_POL—Clock Synchronization

Polarity

When an external clock source is provided to the ADA4255, this bit

is used to configure whether the rising or falling edge is used for

synchronization. The synchronization edge is the edge at which the

ADA4255 performs the chopping. Writing a 1 to this bit synchroniz-

es the ADA4255 to the positive edge of the provided clock. Writing

a 0 synchronizes the ADA4255 to the negative edge of the provided

clock.

Bits[2:0], SYNC[2:0]—Internal Clock Divider

Value

When an external clock is provided to the ADA4255, the SYNC[2:0]

bits set the internal clock divider value. If an external clock is

supplied to the ADA4255, the clock value must be 1 MHz or must

be divided down by the ADA4255 to 1 MHz using the clock divider.

Table 15 lists the available divider values.

Table 15. Clock Divider Values

Divider Value

Bits in the SYNC[2:0] Bit Field

SYNC2

SYNC1

SYNC0

÷1

÷2

÷4

÷8

÷16

÷32

Reserved

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