ADA4255ACPZ-R7 datasheet(30/64 Pages) AD

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Data Sheet

ADA4255

THEORY OF OPERATION

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When configured as an output, GPIO4 can be configured to output

the 1 MHz master clock or the 125 kHz chopping clock. This output

is configured via the INT_CLK_OUT bit (Register SF_CFG) and the

CLK_OUT_SEL bit (Register SYNC_CFG). When configured as an

input, GPIO4 can also accept an external clock. This function is

configured via the EXT_CLK_IN bit (Register SF_CFG).

EXCITATION CURRENTS

The ADA4255 features a configurable excitation current source,

IOUT. This current source can be used to excite external circuitry,

such as resistive bridges or RTD sensors.

The current output is controlled via the EX_CURRENT bits

(Register EX_CURRENT_CFG).

EXTERNAL CLOCK SYNCHRONIZATION

The ADA4255 uses an internal 1 MHz master clock. The master

clock is used to derive the 125 kHz chopping clock used by the

internal amplifiers and the 16 MHz clock used by the charge

pumps.

Either the 1 MHz or the 125 kHz clock can be brought out on the

GPIO4 pin to allow synchronization of external systems. Use the

following procedure to enable the external clock synchronization

feature:

1. Configure GPIO4 as an output by setting Bit 4 in the GPIO_DIR

2. Enable the internal oscillator output special function by setting

the INT_CLK_OUT bit to 1 and the EXT_CLK_ IN bit to 0 in the

SF_CFG register.

3. To output the 125 kHz clock, set the CLK_OUT_SEL bit in the

SYNC_CFG register to 1. To output the 1 MHz clock, set the

CLK_OUT_SEL bit to 0.

The ADA4255 can alternatively be configured to accept an external

clock on GPIO4. The ADA4255 allows external clocks ranging from

1 MHz up to 32 MHz. In the case of an external clock that is

higher than 1 MHz, the input clock must be divided down to 1 MHz

using the internal clock divider. The edge on which the ADA4255

synchronizes can also be configured.

Use the following procedure to configure the ADA4255 to accept an

external clock on GPIO4:

1. Configure GPIO4 as an input by setting Bit 4 in the GPIO_DIR

2. Set the EXT_CLK_IN bit to 1 and ensure that the

INT_CLK_OUT bit is set to 0 in the SF_CFG register.

3. Depending on the frequency of the input clock, configure the

internal clock divider value such that the resulting clock is 1

MHz. The internal clock divider value is controlled by the SYNC

bits in the SYNC_CFG register.

4. For synchronizing on the rising edge, set the SYNC_POL bit in

the SYNC_CFG register to 1. For synchronizing on the falling

edge, set SYNC_POL to 0.

To maintain the performance of the ADA4255, the external clock

must be in the specified range, must always be present, and must

have a duty-cycle of 50%. The quality of the clock used may affect

the device performance. Prevent any overshoot or undershoot on

the clock used, and provide an equal rise and fall to minimize the

impact on the offset voltage.

SEQUENTIAL CHIP SELECT (SCS)

SCS is one of the special functions on the ADA4255 that can

be configured on the GPIOx pins. This mode simplifies isolation

requirements by allowing multiple slave devices to communicate

over the SPI using a single host chip select (CS) line. This commu-

nication also supports cyclical redundancy check (CRC) checksums

transparently.

A GPIO is configured for SCS by first setting the GPIOx pin as

an output using the GPIO_DIR bit (Register GPIO_DIR), and then

setting the respective bit in the SCS register. Configuring a GPIOx

pin for SCS mode is blocked if the GPIOx pin is already configured

for another function from the special functions register, SF_CFG.

When using SCS, the CS signal from the SPI host controller is

provided to the CS pin of the ADA4255. The serial data input (SDI),

serial data output (SDO), and serial clock (SCLK) are shared con-

nections with other SPI devices. The ADA4255 SDO pin supports

tristate operation. Slave SDO pins can be directly connected to

SDO if the slave pins support tristate operation. For slave devices

with SDO pins that do not support tristate operation, an OR gate

can be used to combine the SDO signals. If external logic is used to

combine SDO lines, pull-down or pull-up resistors are recommend-

ed to avoid floating logic gate inputs. Figure 92 and Figure 93

show typical implementations. It is recommended to place pull-up

resistors on the GPIOx pins configured in SCS mode to prevent any

unintended communication with the slave devices when configuring

the ADA4255 in SCS mode.

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