ADA4255ACPZ-R7 datasheet(36/64 Pages) AD

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Data Sheet

ADA4255

DIGITAL INTERFACE

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Rev. 0 | 36 of 64

SPI

The ADA4255 features a 4-wire SPI. This interface operates in SPI

Mode 0 and can be operated with CS tied low. In SPI Mode 0,

SCLK idles low, the falling edge of SCLK is the driving edge, and

the rising edge of SCLK is the sampling edge. This setup means

that data is clocked out on the falling (driving) edge and clocked in

on the rising (sampling) edge.

Figure 98. SPI Mode 0 SCLK Edges

ACCESSING THE ADA4255 REGISTER MAP

The ADA4255 SPI uses 16-bit instructions, plus an optional 8-bit

CRC checksum. Each instruction contains a read or write bit, a

7-bit address, 8 bits of data, and an 8-bit CRC checksum if the

SPI_CRC_ERR bit (Register DIGITAL_ERR) is configured.

Table 8. ADA4255 Instruction Format

R/W

ADDR, Bits[6:0]

Data, Bits[7:0]

CRC, Bits[7:0]

R/W determines whether a read or write operation is performed (1

means read and 0 means write). ADDR, Bits[6:0], is the register

address being read from or written to. R/W and the ADDR, Bits[6:0]

together are referred to as an 8-bit command. For write operations,

DATA, Bits[7:0], is the data being written, and CRC, Bits[7:0], is a

user provided checksum for that data.

The ADA4255 internal address counter is automatically increment-

ed after each read and/or write operation, allowing a continuous

read and/or write mode. After an initial read operation, if CS stays

low, the next 8 SCLK pulses read back the contents of the next

next 8 SCLK pulses load the data on the SDI to the next register

address.

CHECKSUM PROTECTION

The ADA4255 features a checksum mode that can be used to

improve interface robustness. Using the checksum ensures that

only valid data is written to a register and allows data read from a

the SPI_CRC_ERR bit (Register DIGITAL_ERR) trips and no data

is written. To ensure that a register write is successful, the register

contents can be read, and the checksum can be verified.

For CRC checksum calculations, the following polynomial is always

used:

x8 + x2 + x + 1

The SPI_CRC_ERR_DIS bit (Register DIGITAL_ERR) enables and

disables this checksum. The 8-bit checksum is appended to the

end of each read and write transaction. The checksum calculation

for the write transaction is calculated using the 8-bit command

word and the 8-bit data. For a read transaction, the checksum

is calculated using the command word and the 8-bit data output.

Figure 99 and Figure 100 show SPI write and read transactions,

respectively.

In continuous write mode, the first write command CRC is calculat-

ed as described previously in this section. Subsequent CRCs are

clocked in after every register data. The CRC in continuous write

mode is calculated based on the register value it is associated with.

In continuous read mode, the first read command CRC is calculated

as described previously. Subsequent CRCs are clocked out after

every register data. The CRC in continuous read mode is calculated

based only on the register value it is associated with. Figure 101

and Figure 102 show SPI continuous write and read transactions,

respectively.

Figure 99. Writing to a Register with CRC

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