ADA4255ACPZ-R7 datasheet(41/64 Pages) AD

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Data Sheet

ADA4255

APPLICATIONS INFORMATION

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Rev. 0 | 41 of 64

PROGRAMMABLE LOGIC CONTROLLER (PLC)

VOLTAGE AND CURRENT INPUT

The circuit in Figure 107 shows the ADA4255 used to convert a

typical PLC input signal ranges (±10 V, ±5 V, or 20 mA) to an

output voltage from 0 V to +5 V, compatible with high precision

ADCs, such as the AD7768. To perform a voltage measurement,

the ADA4255 input multiplexer is configured to Channel 1, +IN1 and

–IN1, by writing 0x60 to the INPUT_MUX register. The MOSFET

switch must be turned off by setting GPIO0 to logic level low.

GPIO0 must be configured as an output by setting the correspond-

ing bit field to 1 in the GPIO_DIR register. The state of GPIO0 is

controlled by the corresponding bit field in the GPIO_DATA register.

The ADA4255 gain can be configured through the GAIN_MUX

To perform a current measurement, the circuit shown in Figure 107

provides two different shunt resistors, 250 Ω and 100 Ω. To select a

250 Ω resistor, the metal-oxide semiconductor field effect transistor

(MOSFET) switch must be switched on by setting GPIO0 to logic

level high using the GPIO_DATA register. The measurement is

performed using Channel 1 of the ADA4255. To select 100 Ω, the

MOSFET must be turned off by setting GPIO0 to logic level low.

Channel 2 must be selected in this mode by writing 0x18 to the

INPUT_MUX register.

The ADA4255 internal chopping circuitry can be synchronized to

the companion ADC, which keeps the residual chopping noise

at the correct frequency and prevents it from folding back to a

frequency band of interest. To use the synchronization functionality,

configure GPIO4 to be an input by setting the corresponding bit

field in the GPIO_DIR register. Set the ADA4255 to accept an exter-

nal clock by setting the EXT_CLK_IN bit in the SF_CFG register.

Adjust the clock divider such that the resulting clock is equal to 1

MHz. The divider can be adjusted in the SYNC_CFG register. The

SYNC_CFG register also controls the synchronizing edge polarity. It

is recommended that two reads from the M_CLK_CNT register are

performed to ensure that the master clock counter is incrementing,

indicating that the ADA4255 is receiving an external clock.

The ADA4255 on-chip diagnostics allow the user to check the

circuit connections. In PLC applications, the circuit connections are

verified using the wire break detection capabilities of the ADA4255.

The WB_DETECT register flag is set if one of the input connections

is missing. Finally, the CRC check, SCLK counter, and SPI read

and/or write check make the interface more robust as any read

and/or write operations that are not valid are detected. The CRC

check highlights if any bits are corrupted when transmitted between

the processor and the ADA4255.

Figure 107. Voltage and Current Input Application

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