ADA4255ACPZ-R7 datasheet(35/64 Pages) AD

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Data Sheet

ADA4255

THEORY OF OPERATION

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Rev. 0 | 35 of 64

TEST MULTIPLEXER

The ADA4255 contains an internal test multiplexer, as shown in

Figure 96, that connects the inputs of the ADA4255 to useful

voltages. To use the test multiplexer, the C1 and C2 switches must

be closed. These switches are controlled using the INPUT_MUX

ed from any external inputs by opening the A1, A2, B1, and B2

switches.

The TEST_MUX bits in the TEST_MUX register control the test

multiplexer. The test multiplexer can be configured in three different

states as follows:

►

In the default state, the test multiplexer connects the ADA4255

inputs to AVSS. This configuration can be used during a full

system calibration to null out errors, such as offset voltage.

►

The test multiplexer can connect the noninverting input to DVSS

and the inverting input to AVSS, or vice versa. This configuration

can be used to detect any voltage difference between AVSS and

DVSS, which indicates poor connection.

►

The test multiplexer can also provide a +20 mV or −20 mV differ-

ential signal to the inputs of the ADA4255. This configuration can

be used to verify the gain setting of the ADA4255 and the PGIA

functionality without applying an external signal.

EXTERNAL MUX CONTROL

The ADA4255 is able to configure GPIO0 and GPIO1 to control an

external multiplexer. Writes to the EXT_MUX bits in the GAIN_MUX

an external multiplexer. This setup allows amplifier gain and exter-

nal multiplexer settings to be configured with a single SPI write,

avoiding overload conditions. The external mux special function can

be configured via the EXT_MUX_EN bits (Register SF_CFG) and

setting GPIO0 and GPIO1 to outputs, as shown in Figure 97.

Figure 96. Text Multiplexer Connectivity

Figure 97. External Multiplexer Control Example

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