ADA4255ACPZ-R7 datasheet(59/64 Pages) AD

59 / 64 page

Data Sheet

ADA4255

analog.com

Rev. 0 | 59 of 64

TEST MULTIPLEXER REGISTER (TEST_MUX)

DETAILS

Table 29. TEST_MUX Register Details (Register 0x0E)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bit Name

CAL_SEL

CAL_EN[1:0]

TEST_MUX[3:0]

Access

R/W

Reset

Figure 113. Test Multiplexer Connectivity

Bit 7, G5—Output Amplifier Scaling Gain =

1.25 V/V

Clearing Bit G4 to 0 and setting Bit G5 to 1 configures the output

amplifier to a scaling gain value of 1.25 V/V. This setting scales the

input amplifier gain configured in the GAIN_MUX register by

1.25 V/V.

Table 30. Output Amplifier Scaling Gain Settings

Output Amplifier Scaling Gain (V/V)

1.375

1.25

1 X means don't care.

Bit 6, CAL_SEL—Calibration Type

Configuration

Clearing the CAL_SEL bit to 0 configures the ADA4255 to perform

quick calibrations. Setting CAL_SEL to 1 configures the ADA4255

to perform full calibrations.

Bits[5:4], CAL_EN[1:0]—Scheduled Calibration

Enable and Interval

CAL_EN enables scheduled calibrations and configures the interval

on which these calibrations execute. While calibrations are execut-

ing, the inputs of the PGIA are not connected to the input pins.

The CAL_BUSY signal indicates when a calibration is executing.

CAL_BUSY can be output to GPIO2 by configuring GPIO2 as an

output via the GPIO_DIR bits (Register GPIO_DIR) and setting the

CAL_BUSY_OUT bit (Register SF_CFG) to 1. Minimize and avoid

noise and input transients during calibrations.

Table 31. Scheduled Calibration Configurations

CAL_EN, Bit 1

CAL_EN, Bit 0

Scheduled Calibration Configuration

Disabled

Enabled, 33 sec interval

Enabled, 132 sec interval

Enabled, 495 sec interval

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